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All Journal Bulletin of Electrical Engineering and Informatics
Rashmi Shivaswamy
RV University
Electrical & Electronics Engineering

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Hybrid machine learning model towards neuroimaging analysis for detection and grading brain tumors Lakshminarayana Munirathnam; Rashmi Shivaswamy; Suraksha Prakash; Reshma Shafi; Karanam Sunil Kumar
Bulletin of Electrical Engineering and Informatics Vol 15, No 3: June 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v15i3.10988

Abstract

Neuroimaging analysis enables detailed observation of brain tumors, with growing adoption of advanced imaging techniques in clinical practice. Limitations of conventional approaches in supporting proactive decisionmaking and reliable grading are increasingly addressed through machine learning. However, earlier models often faced challenges of limited generalization and computational burden. To overcome these issues, this study introduces a hybrid convolution neural network–support vector machine (CNN–SVM) framework that combines ResNet-50 feature extraction with a feature weighting (FW) strategy and SVM-based classification for improved diagnostic precision. The system is further enhanced with a clinically guided grading scheme, mapping classification outputs into malignant, benign, and healthy categories for greater interpretability. The proposed model was evaluated on three benchmark neuroimaging datasets (Figshare, Kaggle magnetic resonance imaging (MRI), and BraTS-2019) and achieved up to 98.6% accuracy with high sensitivity and specificity, while retaining low computational cost and rapid inference, outperforming conventional CNN-only methods.
Hardware-level data layout approach to mitigate the memory row conflicts on FPGA-based CNN accelerators Shalini Prasad; Suman Jayakumar; Bellary Kursheed; Aruna Mogarala Guruvaya; Rashmi Shivaswamy
Bulletin of Electrical Engineering and Informatics Vol 15, No 4: August 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v15i4.11386

Abstract

Memory row conflicts (MRCs) continue to be a major bottleneck that results in higher latency, ineffective double data rate (DDR) usage, and decreased effective bandwidth in field-programmable gate array (FPGA-based) convolutional neural network (CNN) accelerators. The majority of current effort focuses on computational optimization, frequently ignoring inefficient memory access. In order to reduce memory reference codes (MRCs), this research suggests a hardware-level data layout technique using a memory-centric accelerator architecture. In order to improve hit rates and row buffer locality, the architecture incorporates a dynamic cursor-based address mapping method that adjusts to different feature map sizes across CNN layers and a dual-DDR setup for concurrent data access. The experimental results on VGG16, YOLOv2, and AlexNet show an 18% reduction in MRCs, a 40% increase in throughput, and a 23% decrease in latency compared to state-of-the-art techniques. The design uses a Xilinx Kintex-7 FPGA with low power usage of 1.52 W. The suggested method improves memory performance in FPGA-based CNN accelerators in a scalable and hardware-efficient manner without requiring a large computational burden.
Co-Authors Aruna Mogarala Guruvaya Bellary Kursheed Karanam Sunil Kumar Lakshminarayana Munirathnam Reshma Shafi Shalini Prasad Suman Jayakumar Suraksha Prakash