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Bellary Kursheed
Don Bosco Institute of Technology
Electrical & Electronics Engineering

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Hybrid AI-driven anomaly detection and sequential attack classification for securing IoT networks Gauri Sameer Rapate; Ambuja Krishnappa; Sarala Duggonahalli Veeresh; Karanam Sunil Kumar; Bellary Kursheed
Bulletin of Electrical Engineering and Informatics Vol 15, No 1: February 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v15i1.11048

Abstract

Internet of things (IoT) systems are often inherently heterogeneous and the constantly evolving cyber threat presents a variety of attack vectors that can expose sensitive data across multiple mission-critical applications. The existing intrusion detection methods are often prone to zero-day attacks and specific to limited known intrusions. This paper designs a hybrid and multi level cyber-threat detection framework based on the robust data preprocessing scheme, correlation-based optimal feature selection and integrated anomaly and intrusion detection using a supervised learning approach. In the first stage, a random forest (RF)-based binary anomaly detector is designed as a fast primary threat filter against zero-day threats by detecting traffic anomalies without any prior attack signal. In the second stage, an adaptive, time-aware long short-term memory (LSTM) model performs multi-class intrusion classification using time-lag analysis in traffic flows to accurately identify and classify known attack types with high precision. The proposed framework is evaluated on the network flow telemetry of network–internet of things–version 2 (NF-ToN-IoT-V2) dataset and achieved 99% accuracy in both binary and multiclass settings, with a lower response time of 7.8 ms.
Hardware-level data layout approach to mitigate the memory row conflicts on FPGA-based CNN accelerators Shalini Prasad; Suman Jayakumar; Bellary Kursheed; Aruna Mogarala Guruvaya; Rashmi Shivaswamy
Bulletin of Electrical Engineering and Informatics Vol 15, No 4: August 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v15i4.11386

Abstract

Memory row conflicts (MRCs) continue to be a major bottleneck that results in higher latency, ineffective double data rate (DDR) usage, and decreased effective bandwidth in field-programmable gate array (FPGA-based) convolutional neural network (CNN) accelerators. The majority of current effort focuses on computational optimization, frequently ignoring inefficient memory access. In order to reduce memory reference codes (MRCs), this research suggests a hardware-level data layout technique using a memory-centric accelerator architecture. In order to improve hit rates and row buffer locality, the architecture incorporates a dynamic cursor-based address mapping method that adjusts to different feature map sizes across CNN layers and a dual-DDR setup for concurrent data access. The experimental results on VGG16, YOLOv2, and AlexNet show an 18% reduction in MRCs, a 40% increase in throughput, and a 23% decrease in latency compared to state-of-the-art techniques. The design uses a Xilinx Kintex-7 FPGA with low power usage of 1.52 W. The suggested method improves memory performance in FPGA-based CNN accelerators in a scalable and hardware-efficient manner without requiring a large computational burden.
An efficient ANN-based global maximum power point searching approach for solar PV system under partial shading conditions Lakshminarayana Munirathnam; Yogeesh Amabalagere Chandrashekaraiah; Somu Pundalik Parande; Vani Bengaluru Purushothama; Ramya Mullur Varadhanayaka; Bellary Kursheed
Bulletin of Electrical Engineering and Informatics Vol 15, No 5: October 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v15i5.11597

Abstract

For solar photovoltaic (PV) systems operating in partial shading conditions (PSCs), this research suggests a simplified maximum power point tracking (MPPT) controller based on artificial neural networks (ANNs). By adding multiple local peaks (LPs) to the power-voltage (P-V) curve, PSCs make it impossible for traditional techniques to follow the global maximum power point (GMPP), which results in substantial energy loss and decreased system reliability. In order to overcome this, a DC–DC boost converter's (BC's) duty cycle is adaptively controlled by the suggested ANN-based controller for precise GMPP tracking. Three shading scenarios are used to validate the approach on a 3×2 PV array. According to simulation results, tracking efficiency is higher than 99.4% and overall system efficiency is higher than 99.3%. The ANN greatly reduces oscillations around the GMPP by achieving quick convergence (
Co-Authors Ambuja Krishnappa Aruna Mogarala Guruvaya Gauri Sameer Rapate Karanam Sunil Kumar Lakshminarayana Munirathnam Ramya Mullur Varadhanayaka Rashmi Shivaswamy Sarala Duggonahalli Veeresh Shalini Prasad Somu Pundalik Parande Suman Jayakumar Vani Bengaluru Purushothama Yogeesh Amabalagere Chandrashekaraiah