Article Per Year (5 Year)
p-Index From 2020 - 2025
0.23
P-Index
This Author published in this journals
All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Ramdani, Ahmad Zaky
Unknown Affiliation
Economics, Econometrics & Finance

Published : 1 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 1 Documents
Search

 1 
Implementation of first order statistical processor on FPGA for feature extraction Hadiyoso, Sugondo; Ramdani, Ahmad Zaky; Irawati, Indrarini Dyah; Wijayanto, Inung
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i2.pp234-243

Abstract

Statistical calculations on signals commonly used in feature extraction. In software processing, statistical computation is an easy task. However, providing a computer requires high costs for simple statistical processing. Another consideration is the need for implementation with real-time and portable processing. Therefore, an alternative device is needed, one of which is the field programmable gate array (FPGA). FPGA is a logic circuit board that can be reconfigured according to computing needs. FPGA can also be used as a prototyping of electronic chips. However, implementing statistical formulas in FPGA is interesting in developing its architecture. Therefore, this research proposes a logic circuit design that can be used for first-order statistical calculations. Statistical parameters include the mean, variance, standard deviation, skewness, and kurtosis. The validation test was performed on the electrocardiogram (ECG) signal series and compared with manual calculations. Validation shows that the mean and variance has very high accuracy with an average error of less than 0.06%.
Co-Authors Indrarini Dyah Irawati Inung Wijayanto Sugondo Hadiyoso