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All Journal Indonesian Journal of Cybersecurity and Emerging Risks
Shilpi Bisht
Birla Institute of Applied Sciences, Bhimtal

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Ensuring High Performance During Implementation of Security Algorithms on FPGA Neeraj Bisht; Shilpi Bisht; Sandeep K. Budhani
Indonesian Journal of Cybersecurity and Emerging Risks Vol. 1 No. 2 (2026): 2026: IJCYBER Volume 1 Issue 2 Year 2026
Publisher : Indonesian Artificial Neural Network Society

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Abstract

Cryptography has evolved into an indispensable component of modern technology. To ensure the safety and security of our critical data, which is easily accessible with a single click, it is critical to choose. In addition, comparative research is conducted using the experimental results for various critical adequate, efficient, and viable cryptographic methods. Two widely used cryptography algorithms are the Advanced Encryption Standard and the Data Encryption Standard. The AES and DES algorithms are implemented in FPGA for the Kintex-7 Low voltage at three different frequencies in this study. This research aims to determine which cryptographic method consumes the least amount of power and occupies the least amount of space. It is observed through experimental results that DES consumed 501% more total on-chip power; produced 9.8 % higher junction temperature; required 513 % more Slice LUTs, 294% more Slice Registers, and 373 % more Slices than AES implementation for Kintex-7 Low Voltage at 1.6 GHz frequency. This study indicates that the AES implementation for the Kintex-7 Low Voltage at 1.6 GHz was the most energy and area efficient algorithm, outperforming the DES implementation for the same setup.
Co-Authors Neeraj Bisht Sandeep K. Budhani