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All Journal International Journal of Electrical and Computer Engineering International Journal of Power Electronics and Drive Systems (IJPEDS)
Kannan, Nithiyananthan
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Computer Science & IT Control & Systems Engineering Electrical & Electronics Engineering

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An 8-bit successive-approximation register analog-to-digital converter operating at 125 kS/s with enhanced comparator in 180 nm CMOS technology Zghoul, Fadi Nessir; Al-Bakrawi, Yousra Hussein; Etier, Issa; Kannan, Nithiyananthan
International Journal of Electrical and Computer Engineering (IJECE) Vol 14, No 4: August 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v14i4.pp3830-3854

Abstract

Data converters are necessary for the conversion process of analog and digital signals. Successive approximation register (SAR) analog-to-digital converters (ADC) can achieve high levels of accuracy while consuming relatively low amounts of power and operating at relatively high speeds. This paper describes a design of 8-bit 125 kS/s SAR ADC with a proposed high-speed comparator design based on dynamic latch architecture. The proposed design of the comparator enhances the performance compared to a conventional dynamic comparator by adding two parallel clocked input complementary metal-oxide semiconductor (CMOS) transistors which reduce the parasitic resistance in the latch ground path and serve to minimize the latch delay time. The design of each sub-system for the ADC is explained thoroughly, which contains a sample and hold circuit, successive approximation register, charge redistribution types digital-to-analog converter, and the new proposed comparator. The proposed design is implemented using 180 nm CMOS technology with a power supply of 1.2 V. The average inaccuracy in differential non-linearity (DNL) is +0.6/−0.8 LSB (least significant bit), and integral non-linearity (INL) is +0.4/−0.7 LSB. The proposed design exhibits a delay time of 157 ps at 1 MHz clock frequency.
MATLAB/Simulink based simulations of KY converter for PV panels powered LED lighting system Sureshkumaar, G.; Kannan, Nithiyananthan; Thomas, Sunil
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 10, No 4: December 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (432.587 KB) | DOI: 10.11591/ijpeds.v10.i4.pp1885-1893

Abstract

The main objective of this research work is to develop KY conveter topology for renewable energy sources.Solar energy is the readily available and is the cheapest form of energy. It is non-polluting and environment friendly. The development of high static gain DC-DC converters is an important research area due to the crescent demand of this technology for several applications supplied by low DC output voltage power sources. It is used to provide the uninterruptable power supply and battery powered to the system. So here, step-up DC-DC converters based on the KY converter are proposed for LED lighting systems. The proposed topologies present high voltages and high efficiency for low input voltage and high output voltage applications. The simulation results of the proposed topology have been presented using MATLAB/SIMULINK software.
Co-Authors Al-Bakrawi, Yousra Hussein Etier, Issa Sureshkumaar, G. Thomas, Sunil Zghoul, Fadi Nessir