Article Per Year (5 Year)
p-Index From 2020 - 2025
0.408
P-Index
This Author published in this journals
All Journal International Journal of Reconfigurable and Embedded Systems (IJRES) Journal of Engineering and Technological Sciences
Rahim, Alhan Farhanah Abd
Unknown Affiliation
Aerospace Engineering Automotive Engineering Chemical Engineering, Chemistry & Bioengineering Civil Engineering, Building, Construction & Architecture Economics, Econometrics & Finance Electrical & Electronics Engineering

Published : 2 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 2 Documents
Search

 1 
FPGA in hardware description language based digital clock alarm system with 24-hr format Sayudzi, Mohd Faris Izzwan Mohd; Hamzah, Irni Hamiza; Malik, Azman Ab; Idris, Mohaiyedin; Soh, Zainal Hisham Che; Rahim, Alhan Farhanah Abd; Hadis, Nor Shahanim Mohamad
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i2.pp244-252

Abstract

Currently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 board. Using Verilog HDL language in Quartus Prime 20.1 Lite Edition software, all submodule components is developed and being test benched using ModelSim-Altera Starter Edition 13.1 to ensure the correct functionality. Then all inputs and outputs will be assigned through pin assignment in the software. For verification purpose, it will be downloaded to the Altera DE2-115 board. In conclusion, the file has been successfully implemented to the board and the digital clock with alarm is fully functional as expected. This was proved by the alarm signal, time adjustment and display of the three-display mode which is clock, alarm, and input where each mode carries their own functions as expected.
Wide Bandgap SiC-Based Oxide Thickness Optimization by Computation and Simulation using Enhanced Electron Mobility with Regulated Gate Voltage Technique for High-Power 4H-SiC MOSFET Poobalan, Banu; Hashim, Nuralia Syahida; Natarajan, Manikandan; Rahim, Alhan Farhanah Abd
Journal of Engineering and Technological Sciences Vol. 56 No. 3 (2024)
Publisher : Directorate for Research and Community Services, Institut Teknologi Bandung

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.5614/j.eng.technol.sci.2024.56.3.5

Abstract

This work analyzed the interactions between gate oxide thickness (Tox), voltage dependence, and electron mobility (E-mobility) in the inversion layer, which controls the electron movement properties of 4H-SiC/SiO2. This paper also presents a calculation of gate oxide thickness in correlation with gate voltage mainly for high-voltage applications. The results of this work revealed that at low resistance, E-mobility increases with gate voltage and oxide thickness, which saturates at the point of value. Coulomb scattering and surface phonons at the inversion region of SiC MOSFETs are regarded as the two primary factors that limit E-mobility in these devices. In addition, the high interface trap density (Dit) causes a decrease in E-mobility. The findings from this study confirmed that the computed values of oxide thickness and simulation-based oxide thickness with regulated gate voltages have the least variation below 1%, asserting experimental and theoretical outcomes about the role of oxide thickness and electron movement at the 4H-SiC/SiO2 interfaces. These results indicate that understanding the E-mobility effect on oxide thickness in the SiC MOSFET inversion layer according to gate voltage is important, particularly in achieving an optimal 4H-SiC/SiO2 interface for high-power applications.
Co-Authors Hadis, Nor Shahanim Mohamad Hamzah, Irni Hamiza Hashim, Nuralia Syahida Idris, Mohaiyedin Malik, Azman Ab Natarajan, Manikandan Poobalan, Banu Sayudzi, Mohd Faris Izzwan Mohd Soh, Zainal Hisham Che