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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Hamzah, Irni Hamiza
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Economics, Econometrics & Finance

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FPGA in hardware description language based digital clock alarm system with 24-hr format Sayudzi, Mohd Faris Izzwan Mohd; Hamzah, Irni Hamiza; Malik, Azman Ab; Idris, Mohaiyedin; Soh, Zainal Hisham Che; Rahim, Alhan Farhanah Abd; Hadis, Nor Shahanim Mohamad
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 2: July 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i2.pp244-252

Abstract

Currently, digital clock adapts microprocessor or microcontroller system. Performance of speed and reconfigurability issue become a main concern in digital clocks. New additional feature may be introduced in digital clocks in the future. Field programmable gate array (FPGA) offer better performance of speed and reconfiguration features. Based on these advantages, it is essential to study or explore the digital clock with FPGA design. The objective in this study is to create a hardware description language (HDL)- based digital clock with alarm system and implement it onto the Altera DE2- 115 board. Using Verilog HDL language in Quartus Prime 20.1 Lite Edition software, all submodule components is developed and being test benched using ModelSim-Altera Starter Edition 13.1 to ensure the correct functionality. Then all inputs and outputs will be assigned through pin assignment in the software. For verification purpose, it will be downloaded to the Altera DE2-115 board. In conclusion, the file has been successfully implemented to the board and the digital clock with alarm is fully functional as expected. This was proved by the alarm signal, time adjustment and display of the three-display mode which is clock, alarm, and input where each mode carries their own functions as expected.
Design and implementation of smart traffic light controller with emergency vehicle detection on FPGA Mohamad Hadis, Nor Shahanim; Abdullah, Samihah; Abdul Sukor, Muhammad Ameerul Syafiqie; Hamzah, Irni Hamiza; Setumin, Samsul; Ibrahim, Mohammad Nizam; Azmin, Azwati
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp48-59

Abstract

Increased traffic volumes resulting from urbanization, industrialization, and population growth have given rise to complex issues, including congestion, accidents, and traffic violations at intersections. In the absence of a functional smart traffic light system, traffic congestion occurs due to imbalanced traffic flow at intersections. Current traffic management lacks provisions for ensuring the unobstructed movement of emergency vehicles, even a small delay for which can have significant consequences. This paper presents a smart traffic light controller developed using Verilog hardware description language (HDL) in Quartus Prime 21.1 and Questa Intel field programmable gate array (FPGA) Starter Edition 2021.2, and implemented on an Altera DE2-115 FPGA. The controller is designed specifically to detect emergency vehicle at four-way intersections for inputs radio frequency identification (RFID) readers and infrared (IR) sensors. The RFID readers and IR sensors are managed through slide switches on the FPGA board. The smart traffic light controller contains three sub-modules: clock division, counter, and finite state machine (FSM) operation, enabling it to manage traffic in scenarios with emergency vehicles, high traffic density, and low traffic density. This proposed system can alleviate intersection congestion by controlling access and allocating time effectively. In conclusion, the project ensures the smooth passage of emergency vehicles by continuously monitoring their presence and giving them priority in traffic flow.
Analysing feature selection: impacts towards forecasting electricity power consumption Malik, Azman Ab; Tao, Lyu; Allias, Noormadinah; Hamzah, Irni Hamiza
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp265-272

Abstract

This study focuses on the development of electrical power forecasting based on electricity usage in Wuzhou, China. To develop a forecasting model, the important features need to be identified. Therefore, this study investigates the performance of the feature selection method, focusing on the mutual information as a filter and random forest as a wrapper-based feature selection. From the experiment, six features have been chosen, whereby both feature selection methods chose almost identical features. Later, the selected features are trained and tested with common machine learning models, namely random forest regressor, support vector regression (SVR), k-nearest neighbor (KNN) regressor, and extreme gradient boosting (XGBoost) regressor. The performances of the feature selections tested on each of the models are measured in terms of mean absolute error (MAE), root mean square error (RMSE) and coefficient of determination (R²). Findings from the experiment revealed that XGBoost outperform the other machine learning models with RMSE 0.9566 and R² indicated with 0.2561. However, SVR outperformed XGBoost and other model by obtaining MAE 0.6028. It can be concluded that the performance of filter-based outperformed the embedded feature selection.
Co-Authors Abdul Sukor, Muhammad Ameerul Syafiqie Abdullah, Samihah Allias, Noormadinah Azmin, Azwati Hadis, Nor Shahanim Mohamad Ibrahim, Mohammad Nizam Idris, Mohaiyedin Malik, Azman Ab Mohamad Hadis, Nor Shahanim Rahim, Alhan Farhanah Abd Sayudzi, Mohd Faris Izzwan Mohd Setumin, Samsul Soh, Zainal Hisham Che Tao, Lyu