Article Per Year (5 Year)
p-Index From 2020 - 2025
0.751
P-Index
This Author published in this journals
All Journal International Journal of Electrical and Computer Engineering International Journal of Reconfigurable and Embedded Systems (IJRES)
Mispan, Mohd Syafiq
Unknown Affiliation
Computer Science & IT Economics, Econometrics & Finance Electrical & Electronics Engineering

Published : 4 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 4 Documents
Search

 1 
Systematic review: State-of-the-art in sensor-based abnormality respiration classification approaches Razman, Nur Fatin Shazwani Nor; Nasir, Haslinah Mohd; Zainuddin, Suraya; Brahin, Noor Mohd Ariff; Ibrahim, Idnin Pasya; Mispan, Mohd Syafiq
International Journal of Electrical and Computer Engineering (IJECE) Vol 14, No 6: December 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v14i6.pp6929-6943

Abstract

Respiration-related disease refers to a wide range of conditions, including influenza, pneumonia, asthma, sudden infant death syndrome (SIDS) and the latest outbreak, coronavirus disease 2019 (COVID-19), and many other respiration issues. However, real-time monitoring for the detection of respiratory disorders is currently lacking and needs to be improved. Real-time respiratory measures are necessary since unsupervised treatment of respiratory problems is the main contributor to the rising death rate. Thus, this paper reviewed the classification of the respiratory signal using two different approaches for real-time monitoring applications. This research explores machine learning and deep learning approaches to forecasting respiration conditions. Every consumption of these approaches has been discussed and reviewed. In addition, the current study is reviewed to identify critical directions for developing respiration real-time applications.
A new 13N-complexity memory built-in self-test algorithm to balance static random access memory static fault coverage and test time Jidin, Aiman Zakwan; Hussin, Razaidi; Mispan, Mohd Syafiq; Fook, Lee Weng
International Journal of Electrical and Computer Engineering (IJECE) Vol 15, No 1: February 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v15i1.pp163-173

Abstract

As memories dominate the system-on-chip (SoC), their quality significantly impacts the chip manufacturing yield. There is a growing need to reduce the chip production time and cost, which mainly depends on the testing phase. Hence, a memory built-in self-test (MBIST) utilizing a low-complexity, high-fault-coverage test algorithm is essential for efficient and thorough memory testing. The March AZ1 algorithm, with 13N complexity, was created earlier to balance the test length and fault coverage. However, poor positioning of a write operation in its test sequence caused the reduction of the transition coupling fault (CFtr) detection. This paper presents the creation of the March AZ algorithm, modified from the March AZ1 algorithm, to increase CFtr coverage while preserving the same complexity. It was accomplished by analyzing the fault coverage offered by the March AZ1 algorithm and then reorganizing its test sequence to address the limitation in detecting CFtr. The newly produced March AZ1 algorithm was successfully implemented in an MBIST controller. The simulation tests validated its functionality and demonstrated that the CFtr coverage was enhanced from 62.5% to 75%, achieving an overall fault coverage of 83.3%. Therefore, with 13N complexity, it offers the best fault coverage among all the existing test algorithms with a complexity below 18N.
Low-cost integrated circuit packaging defect classification system using edge impulse and ESP32CAM Kamaruddin, Muhammad Adni; Mispan, Mohd Syafiq; Jidin, Aiman Zakwan; Mohd Nasir, Haslinah; Mohd Nor, Nurul Izza
International Journal of Electrical and Computer Engineering (IJECE) Vol 15, No 1: February 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v15i1.pp156-162

Abstract

Defects in integrated circuit (IC) packaging are inevitable. Several factors can cause defects in IC packaging such as material quality, errors in machine and human handling operations, and non-optimized processes. An automated optical inspection (AOI) is a typical method to find defects in the IC manufacturing field. Nevertheless, AOI requires human assistance in the event of uncertain defect classification. Human inspection often misses very tiny defects and is inconsistent throughout the inspection. Therefore, this study proposed a low-cost IC packaging defect classification system using edge impulse and ESP32-CAM. The method involves training a deep learning model (i.e., convolutional neural network (CNN)) using a dataset of non-defective and defective ICs on Edge Impulse. For defective ICs, the top surface of the ICs is deliberately scratched to imitate the cosmetic defects. ICs with scratch-free on their top surfaces are considered non-defective ICs. A successfully trained model using Edge Impulse is subsequently deployed on ESP32-CAM. The model is optimized to fit the limited resources of the ESP32-CAM. By using the built-in camera in ESP32-CAM, the trained model can perform a real-time image classification of non-defective/defective ICs. The proposed system achieves 86.1% prediction accuracy by using a 1,571 image dataset of defective and non-defective ICs.
FPGA implementation of artificial neural network for PUF modeling Mispan, Mohd Syafiq; Ishak, Mohammad Haziq; Jidin, Aiman Zakwan; Mohd Nasir, Haslinah
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp200-207

Abstract

Field-programmable gate array (FPGA) is a prominent device in developing the internet of things (IoT) application since it offers parallel computation, power efficiency, and scalability. The identification and authentication of these FPGAbased IoT applications are crucial to secure the user-sensitive data transmitted over IoT networks. Physical unclonable function (PUF) technology provides a great capability to be used as device identification and authentication for FPGAbased IoT applications. Nevertheless, conventional PUF-based authentication suffers a huge overhead in storing the challenge-response pairs (CRPs) in the verifier’s database. Therefore, in this paper, the FPGA implementation of the Arbiter-PUF model using an artificial neural network (ANN) is presented. The PUF model can generate the CRPs on-the-fly upon the authentication request (i.e., by a prover) to the verifier and eliminates huge storage of CRPs database in the verifier. The architecture of ANN (i.e., Arbiter-PUF model) is designed in Xilinx system generator and subsequently converted into intellectual property (IP). Further, the IP is programmed in Xilinx Artix-7 FPGA with other peripherals for CRPs generation and validation. The findings show that the Arbiter-PUF model implementation on FPGA using the ANN technique achieves approximately 98% accuracy. The model consumes 12,196 look-up tables (LUTs) and 67 mW power in FPGA.
Co-Authors Aiman Zakwan Jidin Brahin, Noor Mohd Ariff Fook, Lee Weng Hussin, Razaidi Ibrahim, Idnin Pasya Ishak, Mohammad Haziq Kamaruddin, Muhammad Adni Mohd Nasir, Haslinah Mohd Nor, Nurul Izza Nasir, Haslinah Mohd Razman, Nur Fatin Shazwani Nor Zainuddin, Suraya