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All Journal International Journal of Electrical and Computer Engineering International Journal of Reconfigurable and Embedded Systems (IJRES) International Journal of Informatics and Communication Technology (IJ-ICT) Bulletin of Electrical Engineering and Informatics
Mohd Nasir, Haslinah
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Computer Science & IT Economics, Econometrics & Finance Electrical & Electronics Engineering

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Low-cost integrated circuit packaging defect classification system using edge impulse and ESP32CAM Kamaruddin, Muhammad Adni; Mispan, Mohd Syafiq; Jidin, Aiman Zakwan; Mohd Nasir, Haslinah; Mohd Nor, Nurul Izza
International Journal of Electrical and Computer Engineering (IJECE) Vol 15, No 1: February 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v15i1.pp156-162

Abstract

Defects in integrated circuit (IC) packaging are inevitable. Several factors can cause defects in IC packaging such as material quality, errors in machine and human handling operations, and non-optimized processes. An automated optical inspection (AOI) is a typical method to find defects in the IC manufacturing field. Nevertheless, AOI requires human assistance in the event of uncertain defect classification. Human inspection often misses very tiny defects and is inconsistent throughout the inspection. Therefore, this study proposed a low-cost IC packaging defect classification system using edge impulse and ESP32-CAM. The method involves training a deep learning model (i.e., convolutional neural network (CNN)) using a dataset of non-defective and defective ICs on Edge Impulse. For defective ICs, the top surface of the ICs is deliberately scratched to imitate the cosmetic defects. ICs with scratch-free on their top surfaces are considered non-defective ICs. A successfully trained model using Edge Impulse is subsequently deployed on ESP32-CAM. The model is optimized to fit the limited resources of the ESP32-CAM. By using the built-in camera in ESP32-CAM, the trained model can perform a real-time image classification of non-defective/defective ICs. The proposed system achieves 86.1% prediction accuracy by using a 1,571 image dataset of defective and non-defective ICs.
FPGA implementation of artificial neural network for PUF modeling Mispan, Mohd Syafiq; Ishak, Mohammad Haziq; Jidin, Aiman Zakwan; Mohd Nasir, Haslinah
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 1: March 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i1.pp200-207

Abstract

Field-programmable gate array (FPGA) is a prominent device in developing the internet of things (IoT) application since it offers parallel computation, power efficiency, and scalability. The identification and authentication of these FPGAbased IoT applications are crucial to secure the user-sensitive data transmitted over IoT networks. Physical unclonable function (PUF) technology provides a great capability to be used as device identification and authentication for FPGAbased IoT applications. Nevertheless, conventional PUF-based authentication suffers a huge overhead in storing the challenge-response pairs (CRPs) in the verifier’s database. Therefore, in this paper, the FPGA implementation of the Arbiter-PUF model using an artificial neural network (ANN) is presented. The PUF model can generate the CRPs on-the-fly upon the authentication request (i.e., by a prover) to the verifier and eliminates huge storage of CRPs database in the verifier. The architecture of ANN (i.e., Arbiter-PUF model) is designed in Xilinx system generator and subsequently converted into intellectual property (IP). Further, the IP is programmed in Xilinx Artix-7 FPGA with other peripherals for CRPs generation and validation. The findings show that the Arbiter-PUF model implementation on FPGA using the ANN technique achieves approximately 98% accuracy. The model consumes 12,196 look-up tables (LUTs) and 67 mW power in FPGA.
Doppler radar-based pothole sensing using spectral features in k-nearest neighbors Aiman Dani Asmadi, Muhammad; Zainuddin, Suraya; Mohd Nasir, Haslinah; Syafiza Md Isa, Ida; Emileen Abd Rashid, Nur; Pasya, Idnin
Bulletin of Electrical Engineering and Informatics Vol 14, No 1: February 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v14i1.8398

Abstract

Potholes, resulting from wear, weather, and traffic, pose a substantial road safety concern, driving up maintenance costs and government liabilities. Numerous studies have explored pothole detection systems, however, there is a limited focus on radar-based approaches. This study investigates the use of Doppler radar mounted on moving vehicles to collect asphalt road surface data, with the aim to leverage this unique perspective point. Spectral features from power spectral density (PSD) are extracted and explored by incorporating Doppler signal PSD features into a k-nearest neighbors (KNN) within a machine learning framework for road condition classification. Six KNN algorithms are applied, and results indicate that potholes exhibit distinct spectral differences characterized by higher variability, with fine KNN performing the best, achieving an accuracy rate of 95.38% on the test dataset. In summary, this research underscores the effectiveness of Doppler radar-based pothole sensing and emphasizes the significance of algorithm and feature selection for achieving accurate results, proposing the viability of radar systems and machine learning.
Towards efficient fog computing in smart cities: balancing energy consumption and delay Md Isa, Ida Syafiza; Mohd Shaari Azyze, Nur latif Azyze; Mohd Nasir, Haslinah; Rao Gannapathy, Vigneswara; Jayadevan Naidu, Ashwini
International Journal of Informatics and Communication Technology (IJ-ICT) Vol 15, No 1: March 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijict.v15i1.pp332-342

Abstract

In this work, we propose fog-based energy-delay optimization (F-EDO) approach and benchmark its performance against the cloud-based energydelay optimization (C-EDO) method, focusing on energy consumption and delay. Unlike previous studies that optimize energy or delay separately, FEDO minimizes both metrics simultaneously, achieving up to 52.2% energy savings with near-zero delay. Additionally, increasing the number of users also leads to energy savings. This is due to the optimized placement of fog servers at the access layer which reduces network energy consumption compared to C-EDO. F-EDO also significantly reduces delay, with negligible delay compared to C-EDO due to fog servers are placed closer to the users which minimized the transmission distances. Besides, the results also show that the energy saving in F-EDO compared to the C-EDO increased as the processing capacity of the processing server increased while maintaining its minimal delay. Overall, F-EDO proves to be a more energyefficient and lower-delay solution for IoT networks, offering a better alternative to cloud-based offloading.
Co-Authors Aiman Dani Asmadi, Muhammad Aiman Zakwan Jidin Emileen Abd Rashid, Nur Ishak, Mohammad Haziq Jayadevan Naidu, Ashwini Kamaruddin, Muhammad Adni Md Isa, Ida Syafiza Mispan, Mohd Syafiq Mohd Nor, Nurul Izza Mohd Shaari Azyze, Nur Latif Azyze Pasya, Idnin Rao Gannapathy, Vigneswara Syafiza Md Isa, Ida Zainuddin, Suraya