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All Journal Jurnal Ilmiah KOMPUTASI Jurnal Rekayasa elektrika
Atit Pertiwi
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Computer Science & IT Control & Systems Engineering Electrical & Electronics Engineering Energy Engineering

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Analisis Kualitas Media Pembelajaran Daring Edmodo di Sekolah SMK Teratai Putih Gobal 3 Bekasi Berdasarkan Standar ISO 25010 Masroni; Atit Pertiwi
Jurnal Ilmiah KOMPUTASI Vol. 20 No. 4 (2021): Jurnal Ilmiah Komputasi Volume: 20 No. 4, Desember 2021
Publisher : Lembaga Penelitian STMIK Jakarta STI&K

Show Abstract | Download Original | Original Source | Check in Google Scholar

Abstract

SMK Teratai Putih Global 3 Bekasi adalah salah satu sekolah kejuruan di Kota Bekasi yang sudah menggunakan media daring dalam melaksanakan kegiatan pembelajaran yaitu menggunakan aplikasi Edmodo. Dengan aplikasi ini Interaksi yang dilakukan dapat berjalan dengan baik antara guru dan murid dalam melaksanakan kegiatan belajar mengajar, baik pemberian materi, tugas maupun diskusi. Kepuasan suatu tampilan dan performa perangkat lunak diutamakan agar dapat memberikan pelayanan yang baik kepada para siswa guna mendapatkan pendidikan yang berkualitas, sehingga perangkat lunak ini perlu untuk dilakukan analisis kualitasnya. Tujuan dari penelitian ini adalah untuk menganalisis perangkat lunak Edmodo berdasarkan standar ISO 25010 yang terdiri dari 8 (delapan) karakteristik yaitu functional suitability, performance efficiency, reliability, usability, security, portability, compatibility, dan maintainability dengan menggunakan metode kuantitatif. Hasil penelitian yang telah dilakukan adalah pada karakteristik functional suitability menghasilkan nilai X=1, performance efficiency untuk kecepatan rata-rata membuka halaman (93%) dan YSlow (88%), reliability 100%, nilai usability 83,16, security (tingkat keamanan website) berdasarkan tool SUCURI (100%), portability 100%, compatibility 75%.
Desain Layout 1-Stage ADC Pipeline 80Msps dengan Mentor Graphics 0,35µm untuk Aplikasi Kamera Kecepatan Tinggi Hamzah Afandi; Erma Triawati Ch.; Atit Pertiwi
Jurnal Rekayasa Elektrika Vol 10, No 2 (2012)
Publisher : Universitas Syiah Kuala

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (704.648 KB) | DOI: 10.17529/jre.v10i2.141

Abstract

Design layout 1-stage pipeline is part of the 8-stage pipeline 80 Msps ADC. Layout 1-stage pipeline consists of 3 units : op-amp, switch capacitor, precision comparator with latch. Pipeline ADC works gradually and requires synchronization of digital output 8 stage by using a unit delay circuit (D-FF). Pipeline ADC requires pulse rate (clock) generator to support its work. Units OP-AMP transconductance CMOS components designed with the correct specification ADC applications with capacitive loads, with a large input impedance and minimize noise. The precision comparator has Vos (offset voltage) approximately equal to 0V. The capacitor switch designs use NMOS switch as a switch for the sampling and multiplying. In the sampling phase and multiplying processes, the ADC requires a clock pulse with a non-intersect mode (lapping). The width of non-overlapping period was adjusted to the time of constance in the sampling process and multiplying. The total number of each pulse period equal to 12.5 ns or equal to the frequency of 80MHz. In the 1-stage layout an additional correction capacitor was required to correct residual voltage. The total area of the layout 1-stage pipeline ADC is 1-bit 200 μm x 98μm.
Desain Layout 1-Stage ADC Pipeline 80Msps dengan Mentor Graphics 0,35µm untuk Aplikasi Kamera Kecepatan Tinggi Hamzah Afandi; Erma Triawati Ch.; Atit Pertiwi
Jurnal Rekayasa Elektrika Vol 10, No 2 (2012)
Publisher : Universitas Syiah Kuala

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.17529/jre.v10i2.141

Abstract

Design layout 1-stage pipeline is part of the 8-stage pipeline 80 Msps ADC. Layout 1-stage pipeline consists of 3 units : op-amp, switch capacitor, precision comparator with latch. Pipeline ADC works gradually and requires synchronization of digital output 8 stage by using a unit delay circuit (D-FF). Pipeline ADC requires pulse rate (clock) generator to support its work. Units OP-AMP transconductance CMOS components designed with the correct specification ADC applications with capacitive loads, with a large input impedance and minimize noise. The precision comparator has Vos (offset voltage) approximately equal to 0V. The capacitor switch designs use NMOS switch as a switch for the sampling and multiplying. In the sampling phase and multiplying processes, the ADC requires a clock pulse with a non-intersect mode (lapping). The width of non-overlapping period was adjusted to the time of constance in the sampling process and multiplying. The total number of each pulse period equal to 12.5 ns or equal to the frequency of 80MHz. In the 1-stage layout an additional correction capacitor was required to correct residual voltage. The total area of the layout 1-stage pipeline ADC is 1-bit 200 μm x 98μm.
Co-Authors Erma Triawati Christina Hamzah Afandi Masroni