Article Per Year (5 Year)
p-Index From 2020 - 2025
0
P-Index
This Author published in this journals
All Journal PROSIDING SEMINAR NASIONAL Jurnal Rekayasa elektrika
Hamzah Afandi
Unknown Affiliation
Computer Science & IT Control & Systems Engineering Education Electrical & Electronics Engineering Energy Engineering

Published : 8 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 8 Documents
Search

 1 
DESAIN DISKRIT GERBANG LOGIKA NAND 4 MASUKAN BERBASIS TEKNOLOGI CMOS 0,35µ m Dyah Nur’ainingsih; Hamzah Afandi; Widyastuti Widyastuti
PROSIDING SEMINAR NASIONAL & INTERNASIONAL 2018: SEMINAR NASIONAL PENDIDIKAN SAINS DAN TEKNOLOGI
Publisher : Universitas Muhammadiyah Semarang

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (121.564 KB)

Abstract

Dump Accumulator on RFID system built from Register and counter. On the block counter requires a series of NAND, Half Adder, and D flip flop. This paper compares the two discrete schematic designs for a combination of NAND 4  logic  input  gates.  Schematic  design  made  work  at  5Mhz  frequency  and maximum voltage of 3.3volt with Lt spice XVII application software. The first design uses the AND and NAND 2 logic gate combined inputs. The second design uses a NAND 4 logic input gate that is combined from a horizontally arranged (PMOS) and vertical (NMOS) CMOS component. Overall the second design has many advantages over the first design. The simulation results of the two designs show that the first design has advantages in the test of time (speed test), T fall is balanced with T rise is 12ns, total time required 24ns. But power dissipation  is  large  (55,43pW).  While  in  the  second  design,  it  has  a  few advantages of small CMOS components, a simpler schematic design, a small power dissipation (11.15pW), speed at T fall (20ns) larger than T rise (2ns), total time required 22ns. Keywords:   gerbang   logika   NAND,   Desain   diskrit,   Trise,   Tfall,   Power Dissipation
PERANCANGAN DISKRIT D FLIP-FLOP MENGGUNAKAN TEKNOLOGI CMOS 0.35 µm Widyastuti Widyastuti; Hamzah Afandi; Ganjar Febriyani Pratiwi
PROSIDING SEMINAR NASIONAL & INTERNASIONAL 2018: SEMINAR NASIONAL PENDIDIKAN SAINS DAN TEKNOLOGI
Publisher : Universitas Muhammadiyah Semarang

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (316.415 KB)

Abstract

Accumulator dump is one of the tools used to convert serial data into parallel data on RFID communications. Accumulator dump on RFID communication consists of a series of counters and registers, where one of the supporting circuits in the counter and register is D flip-flop. D flip-flops are one type of flip-flop that is built using RS flip-flops. Discrete circuit design Master-slave flip-flops  are  built  using  NAND  logic  gates  built  using  0.35  µ m  CMOS technology. The results of the D flip-flop circuit design are simulated using LT- SPICE software to see the speed of response and power dissipation in the circuit. Keywords: RFID, CMOS 0.35 µ m, D flip-flop, Dump Accumulator, NAND logic
HALF ADDER UNTUK COUNTER PADA METODE DUMP ACCUMULATOR RFID DENGAN TEKNOLOGI 0.35µm Ganjar Febriyani Pratiwi; Hamzah Afandi; Dyah Nur ‘Ainingsih
PROSIDING SEMINAR NASIONAL & INTERNASIONAL 2018: SEMINAR NASIONAL PENDIDIKAN SAINS DAN TEKNOLOGI
Publisher : Universitas Muhammadiyah Semarang

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (107.77 KB)

Abstract

RFID tags are divided into active RFID tags and passive RFID tags. In this case  using  a  passive  RFID  tag  that  is  supported  by  using  a  13.56  MHz frequency radio signal. RFID technology is used here to monitor nutrients in the nursery process in the planting medium. The method used in sending data via the 13.56 MHz radio frequency is the Accumulator Dump method. Accumulator dump is a method to change the output of Delta Sigma ADC in the form of serial data into parallel data. The accumulator dump is built from a series  of  registers  and  counters.  For  the  counter  circuit  itself  uses  a combination of NAND gate circuits, Flip-Flop D circuits and Half Adder (HA) circuits. For the half adder circuit itself, it consists of an EX-OR gate and an AND gate. By using 0.35u technology, this half adder circuit is designed on LT- Spice tools which require an input voltage of 3.3 Volts with 11 PMOS and 11 NMOS, with a value of W = 1u and L = 0.35u to produce the desired output. The frequency of the half adder circuit is 50Hz with a maximum power consumption of 0.00363Watt. Keywords: Tag RFID Pasif, Dump Accumulator, Counter, Half Adder
DESAIN OP-AMP RAIL TO RAIL MENGGUNAKAN TEKNOLOGI CMOS 0.35µm Erfiana Wahyuningsih; Hamzah Afandi; Dyah Nur‘ainingsih
PROSIDING SEMINAR NASIONAL & INTERNASIONAL 2018: SEMINAR NASIONAL PENDIDIKAN SAINS DAN TEKNOLOGI
Publisher : Universitas Muhammadiyah Semarang

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (108.042 KB)

Abstract

Op amp (Operating Amplifier) is a differential amplifier that has a large gain. Op amp is very flexible and easy to apply for various purposes. One is op amp rail to rail, compiled using 0.35u technology with adjusted W and L values to obtain the expected null offset value. Vdd and Vss's short-circuited voltage makes the op amp drive like a rail to a rail or a rail to rail. The output of the op amp rail to rail in the form of swing voltage or swing voltage defines how close the op-amp output can be driven to VDD or VSS (rail to rail). Keywords: Op amp, rail to rail, null offset
PEMBUATAN PROTOTIPE ALAT UKUR KESUBURAN TANAH BERBASIS ARDUINO UNO Hamzah Afandi; Muchamad Eris Rizqul Ulum
PROSIDING SEMINAR NASIONAL & INTERNASIONAL 2018: SEMINAR NASIONAL PENDIDIKAN SAINS DAN TEKNOLOGI
Publisher : Universitas Muhammadiyah Semarang

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (176.924 KB)

Abstract

Soil fertility is a necessity to support a crop’s life, and it affects crop’s growth as well. Based on that, this research to create a prototype to measure soil fertility is conducted. This prototype needs some main components such as an Arduino UNO, iron rod, iron sheeting, a non-inverting op-amp circuit, LCD 16x2 IIC, and a 5V power supply. Arduino UNO acts as a main control on the prototype. The soil fertility sensor is an iron rod and iron sheeting placed parallel to each other. The sensor acts as soil fertility level reader. LCD 16x2 IIC and an LED as an output. Sensor will measure the soil’s fertility and send the information (in voltage) to the non-inverting op-amp circuit to be amplified. The result of this research indicates that sensor can measure soil fertility. Non-inverting op-amp circuit can amplify the received signal and forward the signal to Arduino UNO, which then will be processed and become an LCD and LED output. Voltage measurement result of the humus soil is 643mV and amplified to 1294mV as an ideal soil for crops to be planted. With this prototype, soil fertility can be measured. Keywords Arduino Uno, LED, LCD I2C, OP-AMP CA3140, Kesuburan Tanah
PROTOTYPE PENGUKUR KELEMBABAN TANAH DAN INTENSITAS CAHAYA BERBASIS ARDUINO UNO Dimas Panji Wira Hardi; Hamzah Afandi
PROSIDING SEMINAR NASIONAL & INTERNASIONAL 2018: SEMINAR NASIONAL PENDIDIKAN SAINS DAN TEKNOLOGI
Publisher : Universitas Muhammadiyah Semarang

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (78.812 KB)

Abstract

Innovation is a goal that can play a critical role in the world of technological development, one of which is as a measuring tool for both technical and non- technical fields, among them is to measure moisture in the soil and the sunlight needed by plants in agriculture. This tool requires basic components in the form of Arduino Uno, copper plate, iron plate, non-inverting op-amp circuit, LDR, 16x2 LCD, and a 5V power source. Arduino Uno itself serves as the main control on the tool, LDR, copper plate and iron input block as a reader of moisture content in the soil and sunlight intensity, also 16x2 LCD as an output produ d then yed by . block to determine humidity and light intensity. The copper and iron plates will read the moisture content in the soil and will provide information in the form of an analo signal, as well as the LDR which will ce an analog signal received from the amount of sunlight captured an received by Aduino Uno. After Arduino Uno reads it, then will be displa the LCD in the form of soil moisture percentage and the amount of LUX / Keywords: Soil Moisture, Plant, Arduino Uno, Sun, Light.
Desain Layout 1-Stage ADC Pipeline 80Msps dengan Mentor Graphics 0,35µm untuk Aplikasi Kamera Kecepatan Tinggi Hamzah Afandi; Erma Triawati Ch.; Atit Pertiwi
Jurnal Rekayasa Elektrika Vol 10, No 2 (2012)
Publisher : Universitas Syiah Kuala

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (704.648 KB) | DOI: 10.17529/jre.v10i2.141

Abstract

Design layout 1-stage pipeline is part of the 8-stage pipeline 80 Msps ADC. Layout 1-stage pipeline consists of 3 units : op-amp, switch capacitor, precision comparator with latch. Pipeline ADC works gradually and requires synchronization of digital output 8 stage by using a unit delay circuit (D-FF). Pipeline ADC requires pulse rate (clock) generator to support its work. Units OP-AMP transconductance CMOS components designed with the correct specification ADC applications with capacitive loads, with a large input impedance and minimize noise. The precision comparator has Vos (offset voltage) approximately equal to 0V. The capacitor switch designs use NMOS switch as a switch for the sampling and multiplying. In the sampling phase and multiplying processes, the ADC requires a clock pulse with a non-intersect mode (lapping). The width of non-overlapping period was adjusted to the time of constance in the sampling process and multiplying. The total number of each pulse period equal to 12.5 ns or equal to the frequency of 80MHz. In the 1-stage layout an additional correction capacitor was required to correct residual voltage. The total area of the layout 1-stage pipeline ADC is 1-bit 200 μm x 98μm.
Desain Layout 1-Stage ADC Pipeline 80Msps dengan Mentor Graphics 0,35µm untuk Aplikasi Kamera Kecepatan Tinggi Hamzah Afandi; Erma Triawati Ch.; Atit Pertiwi
Jurnal Rekayasa Elektrika Vol 10, No 2 (2012)
Publisher : Universitas Syiah Kuala

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.17529/jre.v10i2.141

Abstract

Design layout 1-stage pipeline is part of the 8-stage pipeline 80 Msps ADC. Layout 1-stage pipeline consists of 3 units : op-amp, switch capacitor, precision comparator with latch. Pipeline ADC works gradually and requires synchronization of digital output 8 stage by using a unit delay circuit (D-FF). Pipeline ADC requires pulse rate (clock) generator to support its work. Units OP-AMP transconductance CMOS components designed with the correct specification ADC applications with capacitive loads, with a large input impedance and minimize noise. The precision comparator has Vos (offset voltage) approximately equal to 0V. The capacitor switch designs use NMOS switch as a switch for the sampling and multiplying. In the sampling phase and multiplying processes, the ADC requires a clock pulse with a non-intersect mode (lapping). The width of non-overlapping period was adjusted to the time of constance in the sampling process and multiplying. The total number of each pulse period equal to 12.5 ns or equal to the frequency of 80MHz. In the 1-stage layout an additional correction capacitor was required to correct residual voltage. The total area of the layout 1-stage pipeline ADC is 1-bit 200 μm x 98μm.
Co-Authors Atit Pertiwi Dimas Panji Wira Hardi Dyah Nur ‘Ainingsih Dyah Nur‘ainingsih Dyah Nur’ainingsih Erma Triawati Christina Ganjar Febriyani Pratiwi Muchamad Eris Rizqul Ulum Wahyuningsih, Erfiana Widyastuti Widyastuti