V. Kalyanasundaram
SRM Institute of Science and Technology

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Journal : International Journal of Electrical and Computer Engineering

Transformer based NPC multilevel inverter using reduced number of components R. Palanisamy; K. Selvakumar; K. Vijayakumar; D. Karthikeyan; S. Vidyasagar; V. Kalyanasundaram
International Journal of Electrical and Computer Engineering (IJECE) Vol 9, No 6: December 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (14.56 KB) | DOI: 10.11591/ijece.v9i6.pp5150-5158

Abstract

This paper revolves around the reduction of a number of switches and the sources for a multilevel inverter, for this, we have proposed a transformer-based topology which has helped us in reducing the number of switches from twenty-four to sixteen and also in the reduction of sources from eight to one. The circuit consists of two H-Bridges which are coupled by a single-phase transformer, the topology gives us a liberty of changing the number of levels in accordance to the number of turns in the secondary side of the transformer for example if our ratio is 1:1 the number of levels will be five subsequently if it is changed to 1:2 the number of levels will be changed to seven. As the number of switches is reduced the size and complexity of the circuit is also decreased. In order to improve on the part of switching efficiency, we have used space vector pulse width modulation which is a better method as compared to its counterpart switching methods such as sinusoidal pulse width modulation and multiple pulse width modulation techniques.