Article Per Year (5 Year)
p-Index From 2021 - 2026
0.23
P-Index
This Author published in this journals
All Journal International Journal of Electrical and Computer Engineering Bulletin of Electrical Engineering and Informatics Indonesian Journal of Electrical Engineering and Computer Science
Abdul Hadi Abdul Razak
Universiti Teknologi MARA
Computer Science & IT Electrical & Electronics Engineering

Published : 3 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 3 Documents
Search

 1 
Hybrid memristor-CMOS implementation of logic gates design using LTSpice Wan Mohd Hashimi Wan Mohamad Sharif; Mohd Faizul Md Idros; Syed Abdul Mutalib Al-Junid; Fairul Nazmi Osman; Abdul Hadi Abdul Razak; Abdul Karimi Halim; Muhammad Adib Harun
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 3: June 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i3.pp2003-2010

Abstract

In this paper, a hybrid memristor-CMOS implementation of logic gates simulated using LTSpice. Memristors' implementation in computer architecture designs explored in various design structures proposed by researchers from all around the world. However, all prior designs have some drawbacks in terms of applicability, scalability, and performance. In this research, logic gates design based on the hybrid memristor-CMOS structure presented. 2-inputs AND, OR, NAND, NOR, XOR, and XNOR are demonstrated with minimum components requirements. In addition, a 1-bit full adder circuit with high performance and low area consumption is also proposed. The proposed full adder only consists of 4 memristors and 7 CMOS transistors. Half design of the adder base on the memristor component created. Through analysis and simulations, the memristor implementation on designing logic gates using memristor-CMOS structure demonstrated using the generalized metastable switch memristor (MSS) model and LTSpice. In conclusion, the proposed approach improves speed and require less area.
Simulation study of memristor aided logic (MAGIC) based on CMOS NOR gate Wan Mohamad Izzat Wan Zain; Syed Abdul Mutalib Al Junid; Mohd Faizul Md Idros; Abdul Hadi Abdul Razak; Fairul Nazmie Osman; Abdul Karimi Halim; Muhammad Adib Haron
Bulletin of Electrical Engineering and Informatics Vol 9, No 5: October 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (586.297 KB) | DOI: 10.11591/eei.v9i5.2367

Abstract

Memristor is a non-volatile new technology memory where the data stored as a resistance which the performance is influenced by the stateful logic design. Therefore, this study is an attempt to investigate the performance of the MAGIC NOR Gate stateful logic design using LTSPICE and targeted to 2 bits memory application. The objective is to investigate the performance of memristor based stateful logic logic design and schematics for memory application. Furthermore, the study been carried out by implementing the MAGIC NOR gate stateful logic schematic, then simulate the design in order to see the effects of performance including the electrical parameters compared to the others. Evidently, the improvement of MAGIC NOR gate contributes in reducing the number of NOR gate and CMOS count. Besides, the MAGIC NOR gates takes parallel inputs topology and eliminate the threshold voltage compared to IMPLY logic. Nevertheless, larger numbers of memristor required to stable the output consistency in MAGIC NOR gate schematic. 
Performance Evaluation of SW Algorithm on NVIDIA GeForce GTX TITAN X Graphic Processing Unit (GPU) Ahmad Hasif Azman; Syed Abdul Mutalib Al Junid; Abdul Hadi Abdul Razak; Mohd Faizul Md Idros; Abdul Karimi Halim; Fairul Nazmie Osman
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 2: November 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v12.i2.pp670-676

Abstract

Nowadays, the requirement for high performance and sensitive alignment tools have increased after the advantage of the Deoxyribonucleic Acid (DNA) and molecular biology has been figured out through Bioinformatics study. Therefore, this paper reports the performance evaluation of parallel Smith-Waterman Algorithm implementation on the new NVIDIA GeForce GTX Titan X Graphic Processing Unit (GPU) compared to the Central Processing Unit (CPU) running on Intel® CoreTM i5-4440S CPU 2.80GHz. Both of the design were developed using C-programming language and targeted to the respective platform. The code for GPU was developed and compiled using NVIDIA Compute Unified Device Architecture (CUDA). It clearly recorded that, the performance of GPU based computational is better compared to the CPU based. These results indicate that the GPU based DNA sequence alignment has a better speed in accelerating the computational process of DNA sequence alignment.
Co-Authors Abdul Karimi Halim Ahmad Hasif Azman Fairul Nazmi Osman Fairul Nazmie Osman Mohd Faizul Md Idros Muhammad Adib Haron Muhammad Adib Harun Syed Abdul Mutalib Al Junid Syed Abdul Mutalib Al-Junid Wan Mohamad Izzat Wan Zain Wan Mohd Hashimi Wan Mohamad Sharif