Article Per Year (5 Year)
p-Index From 2021 - 2026
0.23
P-Index
This Author published in this journals
All Journal International Journal of Electrical and Computer Engineering TELKOMNIKA (Telecommunication Computing Electronics and Control)
Muhammad Nadzir Marsono
Universiti Teknologi Malaysia
Computer Science & IT Electrical & Electronics Engineering

Published : 4 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 4 Documents
Search

 1 
An FPGA-based network system with service-uninterrupted remote functional update Tze Hon Tan; Chia Yee Ooi; Muhammad Nadzir Marsono
International Journal of Electrical and Computer Engineering (IJECE) Vol 11, No 4: August 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v11i4.pp3222-3228

Abstract

The recent emergence of 5G network enables mass wireless sensors deployment for internet-of-things (IoT) applications. In many cases, IoT sensors in monitoring and data collection applications are required to operate continuously and active at all time (24/7) to ensure all data are sampled without loss. Field-programmable gate array (FPGA)-based systems exhibit a balanced processing throughput and datapath flexibility. Specifically, datapath flexibility is acquired from the FPGA-based system architecture that supports dynamic partial reconfiguration feature. However, device functional update can cause interruption to the application servicing, especially in an FPGA-based system. This paper presents a standalone FPGA-based system architecture that allows remote functional update without causing service interruption by adopting a redundancy mechanism in the application datapath. By utilizing dynamic partial reconfiguration, only the updating datapath is temporarily inactive while the rest of the circuitry, including the redundant datapath, remain active. Hence, there is no service interruption and downtime when a remote functional update takes place due to the existence of redundant application datapath, which is critical for network and communication systems. The proposed architecture has a significant impact for application in FPGA-based systems that have little or no tolerance in service interruption.
Impact of Packet Inter-arrival Time Features for Online Peer-to-Peer (P2P) Classification Bushra Mohammed Ali Abdalla; Mosab Hamdan; Mohammed Sultan Mohammed; Joseph Stephen Bassi; Ismahani Ismail; Muhammad Nadzir Marsono
International Journal of Electrical and Computer Engineering (IJECE) Vol 8, No 4: August 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (910.388 KB) | DOI: 10.11591/ijece.v8i4.pp2521-2530

Abstract

Identification of bandwidth-heavy Internet traffic is important for network administrators to throttle high-bandwidth application traffic. Flow features based classification have been previously proposed as promising method to identify Internet traffic based on packet statistical features. The selection of statistical features plays an important role for accurate and timely classification. In this work, we investigate the impact of packet inter-arrival time feature for online P2P classification in terms of accuracy, Kappa statistic and time. Simulations were conducted using available traces from University of Brescia, University of Aalborg and University of Cambridge. Experimental results show that the inclusion of inter-arrival time (IAT) as an online feature increases simulation time and decreases classification accuracy and Kappa statistic.
Application Profiling and Mapping on NoC-based MPSoC Emulation Platform on Reconfigurable Logic Jia Wei Tang; Yuan Wen Hau; Nasir Shaikh-Husin; Muhammad Nadzir Marsono
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 15, No 3: September 2017
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v15i3.6513

Abstract

In network-on-chip (NoC) based multi-processor system-on-chip (MPSoC) development, application profiling is one of the most crucial step during design time to search and explore optimal mapping. Conventional mapping exploration methodologies analyse application-specific graphs by estimating its runtime behaviour using analytical or simulation models. However, the former does not replicate the actual application run-time performance while the latter requires significant amount of time for exploration. To mapapplications on a specific MPSoC platform, the application behaviour on cycle-accurate emulated platform should be considered for obtaining better mapping quality. This paper proposes an application mapping methodology that utilizes a MPSoC prototyped in Field-Programmable Gate Array (FPGA). Applications are implemented on homogeneous MPSoC cores and their costs are analysed and profiled on the platform in term of execution time, intra-core communication and inter-core communication delays. These metricsare utilized in analytical evaluation of the application mapping. The proposed analytical-based mapping is demonstrated against the exhaustive brute force method. Results show that the proposed method is able to produce quality mappings compared to the ground truth solutions but in shorter evaluation time.
A Customized Reconfiguration Controller with Remote Direct ICAP Access for Dynamically Reconfigurable Platform Tze Hon Tan; Chia Yee Ooi; Muhammad Nadzir Marsono
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 15, No 2: June 2017
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v15i2.5508

Abstract

As FPGA dynamic partial reconfiguration getting into mainstream, design of reconfiguration controller becomes an active research. Most of the existing reconfiguration controllers support only the loading of partial bitstream into configuration memory without allowing user to access ICAP directly, which can provide user higher controllability over the reconfigurable device. This paper presents the architecture of a customized reconfiguration controller with remote direct ICAP access. Remote direct ICAP access allows user to configure or readback device internal registers, which offer user higher controllability over the reconfigurable device. Additionally, the proposed reconfiguration controller achieved at least 3.19 Gbps of reconfiguration throughput, which reduces the platform service downtime during dynamic partial reconfiguration. In order to reduce the latency and transmission overhead of remote functional update, partial bitstream is compressed with run-length encoding before transmission.
Co-Authors Bushra Mohammed Ali Abdalla Chia Yee Ooi Ismahani Ismail Jia Wei Tang Joseph Stephen Bassi Mohammed Sultan Mohammed Mosab Hamdan Nasir Shaikh-Husin Tze Hon Tan Yuan Wen Hau