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All Journal TELKOMNIKA (Telecommunication Computing Electronics and Control) Indonesian Journal of Electrical Engineering and Computer Science
Nasir Shaikh-Husin
Universiti Teknologi Malaysia
Computer Science & IT

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Application Profiling and Mapping on NoC-based MPSoC Emulation Platform on Reconfigurable Logic Jia Wei Tang; Yuan Wen Hau; Nasir Shaikh-Husin; Muhammad Nadzir Marsono
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 15, No 3: September 2017
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v15i3.6513

Abstract

In network-on-chip (NoC) based multi-processor system-on-chip (MPSoC) development, application profiling is one of the most crucial step during design time to search and explore optimal mapping. Conventional mapping exploration methodologies analyse application-specific graphs by estimating its runtime behaviour using analytical or simulation models. However, the former does not replicate the actual application run-time performance while the latter requires significant amount of time for exploration. To mapapplications on a specific MPSoC platform, the application behaviour on cycle-accurate emulated platform should be considered for obtaining better mapping quality. This paper proposes an application mapping methodology that utilizes a MPSoC prototyped in Field-Programmable Gate Array (FPGA). Applications are implemented on homogeneous MPSoC cores and their costs are analysed and profiled on the platform in term of execution time, intra-core communication and inter-core communication delays. These metricsare utilized in analytical evaluation of the application mapping. The proposed analytical-based mapping is demonstrated against the exhaustive brute force method. Results show that the proposed method is able to produce quality mappings compared to the ground truth solutions but in shorter evaluation time.
Algorithm to Convert Signal Interpreted Petri Net Models to Programmable Logic Controller Ladder Logic Diagram Models Z. Aspar; Nasir Shaikh-Husin; M. Khalil-Hani
Indonesian Journal of Electrical Engineering and Computer Science Vol 10, No 3: June 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v10.i3.pp905-916

Abstract

Signal Interpreted Petri Nets (SIPN) modeling has been proposed as an alternative to Ladder Logic Diagram (LLD) modeling for programming complex programmable logic controllers (PLCs) due to its high level of abstraction and functionalities. This paper proposes an algorithm to efficiently convert existing SIPN models to their LLD models equivalences. In order to automate and speed up the conversion process, matrix calculation approach is used. A complex SIPN model was used to show that existing conversion technique must be expanded in order to cater for a more complex SIPN models.
Co-Authors Jia Wei Tang M. Khalil-Hani Muhammad Nadzir Marsono Yuan Wen Hau Z. Aspar