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Abdessamad El Ansari
University of Sidi Mohammed Ben Abdellah Fez
Computer Science & IT Electrical & Electronics Engineering

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An energy-aware system-on-chip architecture for intra prediction in HEVC standard Abdessamad El Ansari; Anas Mansouri; Ali Ahaitouf
International Journal of Electrical and Computer Engineering (IJECE) Vol 9, No 6: December 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (960.781 KB) | DOI: 10.11591/ijece.v9i6.pp5084-5094

Abstract

High resolution 4K and 8K are becoming the more used in video applications. Those resolutions are well supported in the new HEVC standard. Thus, embedded solutions such as development of dedicated ystems-On-Chips (SOC) to accelerate video processing on one chip instead of only software solutions are commendable. This paper proposes a novel parallel and high efficient hardware accelerator for the intra prediction block. This accelerator achieves a high-speed treatment due to pipelined processing units and parallel shaped architecture. The complexity of memory access is also reduced thanks to the proposed design with less increased power consumption. The implementation was performed on the 7 Series FPGA 28 nm technology resources on Zynq-7000 and results show, that the proposed architecture takes 16520 LUTs and can reach 143.65 MHz as a maximum frequency and it is able to support the throughput of 3840×2160 sequence at 90 frames per second.
Co-Authors Ali Ahaitouf Anas Mansouri