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All Journal International Journal of Power Electronics and Drive Systems (IJPEDS)
D. V. Ashok Kumar
Rajeev Gandhi Memorial College of Engineering and Technology affiliated to JNT University, Anantapur
Control & Systems Engineering Electrical & Electronics Engineering

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Implementation of Cascaded based Reversing Voltage Multilevel Inverter using Multi Carrier Modulation Strategies S. Nagaraja Rao; D. V. Ashok Kumar; Ch. Sai Babu
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 9, No 1: March 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (1013.261 KB) | DOI: 10.11591/ijpeds.v9.i1.pp220-230

Abstract

In this paper, a cascaded based reversing voltage (CBRV) multilevel inverter structure is proposed inorder to compensate the major drawbacks in the conventional multilevel inverters. The proposed topology requires less number of components, less carrier signals and gate drives when compared to existing multilevel inverters particularly at higher levels. Therefore, the complexity and overall cost are greatly reduced particularly for higher output voltage levels. This paper also presents the most relevant control and modulation methods by a triangular based multi carrier pulse width modulation (PWM) scheme for the proposed CBRV inverter topology. This paper presents a comparison between different modulation strategies for CBRV inverter topology based on sinusoidal and space vector references with multi triangular carrier waves. The work strive hard to present the scrutiny that has been made between various PWM control techniques for 1–Ф seven level CBRV inverter structure. The comparison is made in terms of Total Harmonic Distortion (THD) and fundamental RMS voltage. Finally, the simulation results are included to verify the effectiveness of the proposed CBRV inverter topology and validate the proposed theory. A hardware set up was developed for a 1–Ф seven level CBRV inverter topology using FPGA based pulse generation.
Co-Authors Ch. Sai Babu S. Nagaraja Rao