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All Journal International Journal of Power Electronics and Drive Systems (IJPEDS)
Amer Chlaihawi
University of Kufa
Control & Systems Engineering Electrical & Electronics Engineering

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A high-performance multilevel inverter with reduced power electronic devices Amer Chlaihawi; Adnan Sabbar; Hur Jedi
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 11, No 4: December 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v11.i4.pp1883-1889

Abstract

This paper introduces a new topology of multilevel inverter, which is able to operate at high performance. This proposed circuit achieves requirements of reduced number of switches, gate-drive circuits, and high design flexibility. In most cases fifteen-level inverters need at least twelve switches. The proposed topology has only ten switches. The inverter has a quasi-sine output voltage, which is formed by level generator and polarity changer to produce the desired voltage and current waveforms. The detailed operation of the proposed inverter is explained. The theoretical analysis and design procedure are given. Simulation results are presented to confirm the analytical approach of the proposed circuit. A 15-level and 31-level multilevel inverters were designed and tested at 50 Hz.
Co-Authors Adnan Sabbar Hur Jedi