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All Journal International Journal of Electrical and Computer Engineering International Journal of Power Electronics and Drive Systems (IJPEDS) Bulletin of Electrical Engineering and Informatics
Adham Hadi Saleh
University of Diyala
Computer Science & IT Control & Systems Engineering Electrical & Electronics Engineering

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Speed Control of PMDCM Based GA and DS Techniques Wisam Najm AL-Din Abed; Adham Hadi Saleh; Abbas Salman Hameed
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 9, No 4: December 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (340.707 KB) | DOI: 10.11591/ijpeds.v9.i4.pp1467-1475

Abstract

Permanent magnet direct current motors (PMDCM) are widely used in various applications such as space technologies, personal computers, medical, military, robotics, electrical vehicles, etc. In this paper, the mathematical model of PMDCM is designed and simulated using MATLAB software. The PMDCM speed is controlled using rate feedback controller due to its ability of improving system damping. To improve the controller performance, it’s parameters are tuned using genetic algorithm (GA) and direct search (DS) techniques. The tuning process based on different performance criteria. The most four common performance criteria used in this paper are JIAE (Integral of Absolute Error), JISE (Integral of Square Error), JITAE (Integral of Time-Weighted Absolute Error), and JITSE (Integral of Time-Weighted Square Error). The results obtained from these evolutionary techniques are compared.  The results show an obvious improvement in system performance including enhancing the transient and steady state of PMDCM speed responses for all performance criteria.
Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process Hayder Khaleel AL-Qaysi; Adham Hadi Saleh; Tahreer Mahmood
International Journal of Electrical and Computer Engineering (IJECE) Vol 12, No 5: October 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v12i5.pp4712-4721

Abstract

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (????????????s) are the highest when compared to other reported FCOTAs in the literature.
Design of CRC circuit for 5G system using VHDL Adham Hadi Saleh; Hayder Khaleel AL-Qaysi; Khalid Awaad Humood; Tahreer Mahmood
Bulletin of Electrical Engineering and Informatics Vol 12, No 4: August 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v12i4.4598

Abstract

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.
A new flying capacitor multilevel converter topology with reduction of power electronic components Rokan Ali Ahmed; Enas Dawood Hassan; Adham Hadi Saleh
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 14, No 2: June 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijpeds.v14.i2.pp1011-1023

Abstract

High power capacity and reliability are characteristics of multilevel inverters. The using a collection of DC sources can produce a terminal voltage that is very close to sinusoidal. The power quality can be improved by adding more levels, but this makes the control system more complicated and expensive. The number of power components in a multilevel inverter has been studied for decades. So, research needs to be done on multilevel inverter configurations to find ways to add levels with fewer power switches than with traditional topologies and those that have already been proposed. In this research, a new power-efficient arrangement of a flying-capacitor inverter is introduced. In order to illustrate the suggested topology, a seven-level multilevel inverter is constructed and demonstrated in a simplified form. Fewer power components, including power switches, capacitors, and gate driver circuits, are required in this topology than in other topologies described in the recent literature, which is one of its main advantages. The improvement mentioned above can be seen in the way this topology works, which is shown by the characteristics of the circuit. MATLAB/Simulink R2021a is used to simulate and verify the circuit to ensure the proposed topology is correct.
Co-Authors Abbas Salman Hameed Enas Dawood Hassan Hayder Khaleel AL-Qaysi Khalid Awaad Humood Rokan Ali Ahmed Tahreer Mahmood Wisam Najm Al-Din Abed