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All Journal International Journal of Electrical and Computer Engineering Bulletin of Electrical Engineering and Informatics Indonesian Journal of Electrical Engineering and Computer Science
Tahreer Mahmood
University of Diyala
Computer Science & IT Electrical & Electronics Engineering

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Design methodology for general enhancement of a single-stage self-compensated folded-cascode operational transconductance amplifiers in 65 nm CMOS process Hayder Khaleel AL-Qaysi; Adham Hadi Saleh; Tahreer Mahmood
International Journal of Electrical and Computer Engineering (IJECE) Vol 12, No 5: October 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v12i5.pp4712-4721

Abstract

The problems resulting from the use of nano-MOSFETs in the design of operational trans-conductance amplifiers (OTAs) lead to an urgent need for new design techniques to produce high-performance metrics OTAs suitable for very high-frequency applications. In this paper, the enhancement techniques and design equations for the proposed single-stage folded-cascode operational trans-conductance amplifiers (FCOTA) are presented for the enhancement of its various performance metrics. The proposed single-stage FCOTA adopts the folded-cascode (FC) current sources with cascode current mirrors (CCMs) load. Using 65 nm complementary metal-oxide semiconductor (CMOS) process from predictive technology model (PTM), the HSPICE2019-based simulation results show that the designed single-stage FCOTA can achieve a high open-loop differential-mode DC voltage gain of 65.64 dB, very high unity-gain bandwidth of 263 MHz, very high stability with phase-margin of 73°, low power dissipation of 0.97 mW, very low DC input-offset voltage of 0.14 uV, high swing-output voltages from −0.97 to 0.91 V, very low equivalent input-referred noise of 15.8 nV/Hz, very high common-mode rejection ratio of 190.64 dB, very high positive/negative slew-rates of 157.5/58.3 V⁄us, very fast settling-time of 5.1 ns, high extension input common-mode range voltages from −0.44to 1 V, and high positive/negative power-supply rejection ratios of 75.5/68.8 dB. The values of the small/large-signal figures-of-merits (????????????s) are the highest when compared to other reported FCOTAs in the literature.
Evaluation of different quantization resolution levels on the BER performance of massive MIMO systems under different operating scenarios Hayder Khaleel AL-Qaysi; Tahreer Mahmood; Khalid Awaad Humood
Indonesian Journal of Electrical Engineering and Computer Science Vol 23, No 3: September 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v23.i3.pp1493-1500

Abstract

The massive MIMO system is one of the main technologies in the fifth generation (5G) of telecommunication systems, also recognized as a highly large-scale system. Constantly in massive MIMO systems, the base station (BS) is provided with a large number of antennas, and this large number of antennas need high-quantization resolution levels analog-to-digital converters (ADCs). In this situation, there will be more power consumption and hardware costs. This paper presents the simulation performance of a suggested method to investigate and analyze the effects of different quantization resolution levels of ADCs on the bit error rate (BER) performance of massive MIMO system under different operating scenarios using MATLAB software. The results show that the SNR exceeds 12 dB accounts for only 0.001% of BER signals when the number of antennas 60 with low quantization a 2 bits’ levels ADCs, approximately. But when the antenna number rises to 300, the SNR exceeds 12 dB accounts for almost 0.01% of BER transmitted signals. Comparably with the BER performance of high quantization, 4 bits-quantization resolution levels ADCs with the same different antennas have a slight degradation. Therefore, the number of antennas is a very important influence factor.
Design of CRC circuit for 5G system using VHDL Adham Hadi Saleh; Hayder Khaleel AL-Qaysi; Khalid Awaad Humood; Tahreer Mahmood
Bulletin of Electrical Engineering and Informatics Vol 12, No 4: August 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v12i4.4598

Abstract

In this document, we focus on how to design cyclic redundancy check (CRC) circuits with different 5G polynomial divisor using very high-speed integrated circuit (VHSIC) hardware description language (VHDL) to integrate in field-programmable gate array (FPGA) suitable kit using a suitable design code. The different between designed circuits came from the different of data size according to polynomials requirements conditions since there are huge data size in 5G system that required divide it with suitable method and then implemented the required circuit. CRC code as a polar code and short low density parity check (LDPC) is proposed in 5G new radio (NR) systems, CRC properties to divided data and CRC cod make it particularly very useful for codes with higher data rate and longer lengths, and for codes with low data rates and small length as an error detection method. The CRC encoder circuit (transmitter side) and CRC decoder circuit (receiver side) with different polynomial and data size have been designed using VHDL. Xilinx ISE 14.3 simulator, where the test bench simulation results give the expected simulator results of proposed decoding circuit scheme so to integrated using ZYNQ FPGA kit.
Co-Authors Adham Hadi Saleh Hayder Khaleel AL-Qaysi Khalid Awaad Humood