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All Journal International Journal of Power Electronics and Drive Systems (IJPEDS) International Journal of Advances in Applied Sciences Indonesian Journal of Electrical Engineering and Computer Science
T.S. Anandhi
Annamalai University
Control & Systems Engineering Earth & Planetary Sciences Electrical & Electronics Engineering Environmental Science Materials Science & Nanotechnology Mathematics Physics

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 1 
Real Time Implementation of Variable Step Size Based P&O MPPT for PV Systems Based on dSPACE K. Muthukumar; T.S. Anandhi
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 7, No 3: September 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (569.741 KB) | DOI: 10.11591/ijpeds.v7.i3.pp915-925

Abstract

Nowadays Solar energy is an important energy source due to the energy crisis and environment pollution. Maximum power point tracking (MPPT) algorithm improves the utilization efficiency of a photovoltaic systems. In this paper an improved P&O MPPT algorithm is developed and simulated using MATLAB / SIMULINK to control the DC/DC buck converter. The obtained simulink model is also verified using dspace tool. Both the simulated and experimental results are validated by also comparing them with conventional MPPT methods. The performance measures show the increase in the efficiency of PV system by the proposed model.
Simulation and dSPACE Based Implementation of Various PWM Strategies for A New H-Type FCMLI Topology Chinnapettai Ramalingam Balamurugan; S.P. Natarajan; T.S. Anandhi; B. Shanthi
International Journal of Power Electronics and Drive Systems (IJPEDS) Vol 6, No 3: September 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (436.167 KB) | DOI: 10.11591/ijpeds.v6.i3.pp615-624

Abstract

Depending on the number of levels in output voltage, inverters can be divided into two categories: two level inverter and Multi Level Inverters (MLIs). An inverter topology for high voltage and high power applications that seems to be gaining interest is the MLI. In high power and high voltage applications, the two level inverters have some limitations in operating at high frequency mainly due to switching losses and constraints of device rating.In this paper, a three phase H + type FCMLI (Flying Capacitor MLI) using sinusoidal reference, third harmonic injection reference, 60 degree reference and stepped wave reference are initially developed using SIMULINK and then implemented in real time environment using dSPACE. In H-type FCMLI with R-load it is inferred that bipolar COPWM-C provides output with relatively low distortion for 60 degree reference and bipolar COPWM-C strategy is found to perform better since it provides relatively higher fundamental RMS output voltage for THI reference. The five level output voltages of the chosen MLIs obtained using the MATLAB and dSPACE based PWM (Pulse Width Modulation) strategies and the corresponding %THD (Total Harmonic Distortion), VRMS (fundamental), CF (Crest Factor) and FF (Form Factor) are presented and analyzed.
Design of A New Three Phase Hybrid H-bridge and H-Type FCMLI for Various PWM Strategies Chinnapettai Ramalingam Balamurugan; S.P. Natarajan; V. Padmathilagam; T.S. Anandhi
International Journal of Advances in Applied Sciences Vol 4, No 3: September 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (561.1 KB) | DOI: 10.11591/ijaas.v4.i3.pp82-89

Abstract

The inverters have to be designed to obtain a quality output voltage or a current waveform with a minimum amount of ripple content. In high power and high voltage applications the conventional two level inverters, however, have some limitations in operating at high frequency mainly due to switching losses and constraints of the power device ratings. Series and parallel combination of power switches in order to achieve the power handling voltages and currents. The conventional two level inverters produce THD levels around 60% even under normal operating conditions which are undesirable and cause more losses and other power quality problems too on the AC drives and utilities. Nowadays, multilevel inverters are widely used in power industry. Voltage unbalance problem is one of the major issues in working of multilevel inverter. In this paper, a three phase H-bridge + H-type FCMLI using sinusoidal reference, third harmonic injection reference, 60 degree reference and stepped wave reference are initially developed using SIMULINK and then implemented in real time environment using dSPACE. The five level output voltages of the chosen MLIs obtained using the MATLAB and dSPACE based PWM strategies and the corresponding % THD, VRMS (fundamental) , CF and FF are presented and analyzed. It is observed that bipolar COPWM-C provides output with relatively low distortion for sine reference and bipolar COPWM-B strategy is found to perform better since it provides relatively higher fundamental RMS output voltage for 60 degree reference.
Hardware Implementation of Cascaded Hybrid Multilevel Inverter with Reduced Number of Switches Chinnapettai Ramalingam Balamurugan; S.P. Natarajan; T.S. Anandhi; R. Bensaraj
Indonesian Journal of Electrical Engineering and Computer Science Vol 3, No 2: August 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v3.i2.pp314-322

Abstract

This paper presents the comparison of various multicarrier Pulse Width Modulation (PWM) techniques for the Cascaded Hybrid Multi Level Inverter (CHBMLI). Due to switch combination redundancies, there are certain degrees of freedom to generate the five level AC output voltage. This paper presents the use of Control Freedom Degree (CFD) combination. The effectiveness of the PWM strategies developed using CFD are demonstrated by simulation and experimentation.  The simulation results indicate that the chosen five level inverter triggered by the developed Phase Disposition(PD), Phase Opposition and Disposition(POD), Alternate Phase Opposition and Disposition (APOD), Carrier Overlapping (CO), Phase Shift (PS) and Variable Frequency (VF) PWM strategies developed are implemented in real time using FPGA. The simulation and experimental outputs closely match with each other validating the strategies presented.
A Nine Level Cascaded Multi Level Inveter Using Embedded and FlipFlops Chinnapettai Ramalingam Balamurugan; S.P. Natarajan; T.S. Anandhi; B. Shanthi
Indonesian Journal of Electrical Engineering and Computer Science Vol 15, No 1: July 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar

Abstract

This paper proposes a nine level cascaded multilevel inverter based on the flip flops and logic gates. Generally multilevel inverter is used to achieve the high power by using a series of power semiconductor switches with the several dc voltage sources which is used to perform the power conversion. In this paper the flip flop based CMLI is compared with the conventional CMLI. The flip flops and logic gates are used to create logic equation for the each switch of the CMLI by using the switching states. This proposed topology is mainly used to reduce the total harmonic distortion and also increase the performance of the system. DOI: http://dx.doi.org/10.11591/telkomnika.v15i1.7978
Performance Evaluation of 3Φ Asymmetrical MLI with Reduced Switch Count Chinnapettai Ramalingam Balamurugan; S.P. Natarajan; T.S. Anandhi
Indonesian Journal of Electrical Engineering and Computer Science Vol 3, No 3: September 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v3.i3.pp671-680

Abstract

The multi level inverter system is habitually exploited in AC drives, when both reduced harmonic contents and high power are required. In this paper, a new topology for three phase asymmetrical multilevel inverter employing reduced number of switches is introduced. With less number of switches, the cost, space and weight of the circuit are automatically reduced. This paper discusses the new topology, the switching strategies and the operational principles of the chosen inverter. Simulation is carried out using MATLAB-SIMULINK. Various conventional PWM techniques that are appropriate to the chosen circuit such as PDPWM, PODPWM, APODPWM, VFPWM and COPWM are employed in this work. COPWM technique affords the less THD value and also affords a higher fundamental RMS output voltage.
Co-Authors B. Shanthi Chinnapettai Ramalingam Balamurugan K. Muthukumar R. Bensaraj S.P. Natarajan V. Padmathilagam