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Journal : Indonesian Journal of Electrical Engineering and Computer Science

Hardware Implementation of Cascaded Hybrid Multilevel Inverter with Reduced Number of Switches Chinnapettai Ramalingam Balamurugan; S.P. Natarajan; T.S. Anandhi; R. Bensaraj
Indonesian Journal of Electrical Engineering and Computer Science Vol 3, No 2: August 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v3.i2.pp314-322

Abstract

This paper presents the comparison of various multicarrier Pulse Width Modulation (PWM) techniques for the Cascaded Hybrid Multi Level Inverter (CHBMLI). Due to switch combination redundancies, there are certain degrees of freedom to generate the five level AC output voltage. This paper presents the use of Control Freedom Degree (CFD) combination. The effectiveness of the PWM strategies developed using CFD are demonstrated by simulation and experimentation.  The simulation results indicate that the chosen five level inverter triggered by the developed Phase Disposition(PD), Phase Opposition and Disposition(POD), Alternate Phase Opposition and Disposition (APOD), Carrier Overlapping (CO), Phase Shift (PS) and Variable Frequency (VF) PWM strategies developed are implemented in real time using FPGA. The simulation and experimental outputs closely match with each other validating the strategies presented.
A Nine Level Cascaded Multi Level Inveter Using Embedded and FlipFlops Chinnapettai Ramalingam Balamurugan; S.P. Natarajan; T.S. Anandhi; B. Shanthi
Indonesian Journal of Electrical Engineering and Computer Science Vol 15, No 1: July 2015
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar

Abstract

This paper proposes a nine level cascaded multilevel inverter based on the flip flops and logic gates. Generally multilevel inverter is used to achieve the high power by using a series of power semiconductor switches with the several dc voltage sources which is used to perform the power conversion. In this paper the flip flop based CMLI is compared with the conventional CMLI. The flip flops and logic gates are used to create logic equation for the each switch of the CMLI by using the switching states. This proposed topology is mainly used to reduce the total harmonic distortion and also increase the performance of the system. DOI: http://dx.doi.org/10.11591/telkomnika.v15i1.7978
Performance Evaluation of 3Φ Asymmetrical MLI with Reduced Switch Count Chinnapettai Ramalingam Balamurugan; S.P. Natarajan; T.S. Anandhi
Indonesian Journal of Electrical Engineering and Computer Science Vol 3, No 3: September 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v3.i3.pp671-680

Abstract

The multi level inverter system is habitually exploited in AC drives, when both reduced harmonic contents and high power are required. In this paper, a new topology for three phase asymmetrical multilevel inverter employing reduced number of switches is introduced. With less number of switches, the cost, space and weight of the circuit are automatically reduced. This paper discusses the new topology, the switching strategies and the operational principles of the chosen inverter. Simulation is carried out using MATLAB-SIMULINK. Various conventional PWM techniques that are appropriate to the chosen circuit such as PDPWM, PODPWM, APODPWM, VFPWM and COPWM are employed in this work. COPWM technique affords the less THD value and also affords a higher fundamental RMS output voltage.