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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
R. Jayachira
Arunai Engineering College
Economics, Econometrics & Finance

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Design and Analysis of CMOS and Adiabatic 1:16 Multiplexer and 16:1 Demultiplexer K. Anitha; R. Jayachira
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 5, No 1: March 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (1368.145 KB) | DOI: 10.11591/ijres.v5.i1.pp8-17

Abstract

Conventional CMOS is compared with two adiabatic logic styles namely Efficient Charge Recovery Logic (ECRL) and Improved Efficient Charge Recovery Logic (IECCRL). A 16:1 multiplexer and 1:16 demultiplexer using these design techniques are designed and results are compared based on their minimum/maximum power consumption and transistor count. The proposed schematics multiplexer and demultiplexer are simulated using Microwind2 and DSCH2 software.
Co-Authors K. Anitha