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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Tan Wee Xin Wilson
Multimedia University
Economics, Econometrics & Finance

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Low power 11T adder comparator design C.M.R. Prabhu; Tan Wee Xin Wilson; T. Bhuvaneswari
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 9, No 1: March 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (434.445 KB) | DOI: 10.11591/ijres.v9.i1.pp28-33

Abstract

Comparator is a basic arithmetic component in a digital system and adders are the basic block of processor unit, the performance of adder will improve the system performance. The proposed 11T adder comparator is consists of three main components, namely XOR, inverter, and MUX logic. The circuit is designed and implemented based on top-down approach with 11 transistors. The proposed cell can be used at higher temperature with minimal power loss. It also gives faster response for the carry output. The proposed comparator circuit shows 63.80% improvement in power consumption than other circuits.
Co-Authors C.M.R. Prabhu T. Bhuvaneswari