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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
M. A. Gaikwad
B.D.C.E. Sewargram, Wardha(M.S.)
Economics, Econometrics & Finance

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Design of Mesh and Torus Topologies for Network-On-Chip Application Sonal S. Bhople; M. A. Gaikwad
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 2, No 2: July 2013
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (150.851 KB) | DOI: 10.11591/ijres.v2.i2.pp76-82

Abstract

Network-on-Chip (NoC) is a general purpose on-chip communication concept that offers high throughput, which is the basic requirement to deal with complexity of modern systems. In Network on chip topology design is one of the significant factors that affect the net delay of the system. In this paper mesh topology and torus topology are compared in terms of network delay for a given NOC application using Xillinc 9.1c.
Co-Authors Sonal S. Bhople