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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
N. Madhur
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Economics, Econometrics & Finance

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Verilog based efficient convolution encoder and viterbi decoder Md. Abdul Rawoof; Umasankar Ch.; D. Naresh Kumar; D. Khalandar Basha; N. Madhur
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (391.907 KB) | DOI: 10.11591/ijres.v8.i1.pp75-80

Abstract

In the today’s digital communication Systems, transmission of data with more reliability and efficiency is the most challenging issue for data communication through channels. In communication systems, error correction technique plays a vital role. In error correction techniques, The capacity of data can be enhanced by adding the redundant information for the source data while transmitting the data through channel. It mainly focuses on the awareness of convolution encoder and Viterbi decoder. For decoding convolution codes Viterbi algorithm is preferred.
Co-Authors D. Khalandar Basha D. Naresh Kumar Md. Abdul Rawoof Umasankar Ch.