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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Nagarjuna T
Institute of Aeronautical Engineering
Economics, Econometrics & Finance

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Analysis of CMOS Logic and Transmission Gate for 64 Bit Parallel Prefix Adders Nehru.K K; Nagarjuna T; Somanaidu U
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 7, No 2: July 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (830.829 KB) | DOI: 10.11591/ijres.v7.i2.pp115-123

Abstract

Parallel prefix adder network is a type of carry look ahead adder structure. It is widely considered as the fastest adder and used for high performance arithmetic circuits in the digital signal processors. In this article, an introduction to the design of 64 bit parallel prefix adder using transmission technique which acquires least no of nodes with the lowest transistor count and low power consumption is presented. The 64 bit parallel prefix adder is designed and comparison is made between other previously parallel prefix adders. The result shows that the proposed 64 bit parallel prefix adder is slightly better than existing parallel prefix adders and it considerably increases the computation speed.The spice tool is used for analysis with different supply voltages.
Co-Authors Nehru.K K Somanaidu U