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All Journal TELKOMNIKA (Telecommunication Computing Electronics and Control) Indonesian Journal of Electrical Engineering and Computer Science
Ng Yen Phing
University Malaysia Perlis
Computer Science & IT

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Topology Design of Extended Torus and Ring for Low Latency Network-on-Chip Architecture Ng Yen Phing; M. N. Mohd Warip; Phaklen Ehkan; F. W. Zulkefli; R. Badlishah Ahmad
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 15, No 2: June 2017
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v15i2.6134

Abstract

In essence, Network-on-Chip (NoC) also known as on-chip interconnection network has been proposed as a design solution to System-on-Chip (SoC). The routing algorithm, topology and switching technique are significant because of the most influential effect on the overall performance of Network-on-Chip (NoC). Designing of large scale topology alongside the support of deadlock free, low latency, high throughput and low power consumption is notably challenging in particular with expanding network size. This paper proposed an 8x8 XX-Torus and 64 nodes XX-Ring topology schemes for Network-on-Chip to minimize the latency by decrease the node diameter from the source node to destination node. Correspondingly, we compare in differences on the performance of mesh, full-mesh, torus and ring topologies with XX-Torus and XX-Ring topologies in term of latency. Results show that XX-Ring outperforms the conventional topologies in term of latency. XX-Ring decreases the average latency by 106.28%, 14.80%, 6.7 1%, 1.73%, 442.24% over the mesh, fully-mesh, torus, XX-torus, and Ring topologies.
Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture Ng Yen Phing; M.N.Mohd Warip; Phaklen Ehkan; R Badlishah Ahmad; F.W. Zulkefli
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp802-809

Abstract

The size of the transistor has reached physical processor limitation in particular for traditional bus-based and point-to-point architecture in system-on-chip (SoC). Therefore, network-on-chip (NoC) was proposed as a solution. The performances required for the optimization of the NoC are low network latency, low power consumption, small area, and high throughput. However, recently the size of the NoC architecture has increased and the communication between cores to core become complicated. To overcome this disadvantages, topology plays an important role. In this paper, we reduce the number of the router in the 16 cores and 64 cores ring and mesh topologies by connected more numbers of node in each router. Result shows that reducing the number of the router in 64 cores ring topology outperforms the conventional topologies in term of area, power consumption, latency, and accepted packet rate. Reducing router in 64 cores ring topology decrease the average area, power consumption, latency, and increase the average accepted packet rate by 160.45%, 23.88%, 54.76%, and 223.88% over the 64 cores mesh, reducing router in mesh, ring, and cross-link mesh topologies.
Co-Authors F. W. Zulkefli F.W. Zulkefli M. N. Mohd Warip M.N.Mohd Warip Phaklen Ehkan R Badlishah Ahmad R. Badlishah Ahmad