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All Journal TELKOMNIKA (Telecommunication Computing Electronics and Control)
Shaik Asif Hussain
Middle East College
Computer Science & IT

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A Hardware Model to Measure Motion Estimation with Bit Plane Matching Algorithm Shaik Asif Hussain; Chandrashekar Ramaiah; S. Javeed Hussain
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 16, No 5: October 2018
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v16i5.7672

Abstract

The multistep approach involving combination of techniques is referred as motion estimation. The proposed approach is an adaptive control system to measure the motion from starting point to limit of search. The motion patterns are used to analyze and avoid stationary regions of image. The algorithm proposed is robust efficient and the calculations justify its advantages. The motivation of the work is to maximize the encoding speed and visual quality with the help of motion vector algorithm. In this work a hardware model is developed in which a frame of pictures are captured and sent via serial port to the system. MATLAB simulation tool is used to detect the motion among the picture frame. Once any motion is detected that signal is sent to the hardware which will give the appropriate sign accordingly. This system is developed on two platforms (hardware as well software) to estimate and measure the motion vectors.
A hybrid soft bit flipping decoder algorithm for effective signal transmission and reception Shaik Asif Hussain; Jyothi Chinna Babu; Raza Hasan; Salman Mahmood
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 20, No 3: June 2022
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v20i3.23300

Abstract

The Euclidean geometry (EG) based low-density parity check (LDPC) codes are enciphered and deciphered in various modes. These algorithms have the back-and-forth between decoding delay, and power usage, device unpredictability resources, and error rate efficacy are all available with these methods. As a result, the goal of this paper is to develop a comprehensive method to describe both soft and burst error bits for optimal data transfer. As a result, for EG-LDPC codes, a hybrid soft bit flipping (HSBF) decoder is suggested, which decreases decoding complications while improving message data transfer. A simulation model is formed using Xilinx synthesis report to study decoding latency, hardware usage, and power usage. A HSBF decoder is used in this paper, which accepts a 64-bit coding sequence and assigns 64 Adjustable nodes to it. It checks all customizable cluster connections and quantifies adjustable node values and actions. As a consequence of the data collected, our simulation model demonstrates that the HSBF technique outperforms soft bit flipping (SBF) algorithms. As a result, the techniques are ideal for usage in intermediate applications and as well as in cyber security processing technologies, medical applications.
Co-Authors Chandrashekar Ramaiah Jyothi Chinna Babu Raza Hasan S. Javeed Hussain Salman Mahmood