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All Journal Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics Bulletin of Electrical Engineering and Informatics
A. S. M. Zain
Universiti Teknikal Malaysia Melaka (UTeM)
Computer Science & IT Electrical & Electronics Engineering Engineering

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Journal : Bulletin of Electrical Engineering and Informatics

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Performance analysis of ultrathin junctionless double gate vertical MOSFETs K. E. Kaharudin; Z. A. F. M. Napiah; F. Salehuddin; A. S. M. Zain; Ameer F. Roslan
Bulletin of Electrical Engineering and Informatics Vol 8, No 4: December 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (665.525 KB) | DOI: 10.11591/eei.v8i4.1615

Abstract

The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.
Co-Authors Ameer F. Roslan F. Salehuddin K. E. Kaharudin Z. A. F. M. Napiah