Garuda - Garba Rujukan Digital

Analysis of analog and RF behaviors in junctionless double gate vertical MOSFET K. E. Kaharudin; Z. A. F. M. Napiah; F. Salehuddin; A. S. M. Zain; Ameer F. Roslan
Bulletin of Electrical Engineering and Informatics Vol 9, No 1: February 2020
Publisher : Institute of Advanced Engineering and Science

The prime obstacle in continuing the transistor’s scaling is to maintain ultra-shallow source/drain (S/D) junctions with high doping concentration gradient, which definitely demands an advanced and complicated S/D and channel engineering. Junctionless transistor configuration has been found to be an alternative device structure in which the junction and doping gradients could be totally eliminated, thus simplifying the fabrication process. In this paper, a process simulation has been performed to study the impact of junctionless configuration on the analog and RF behaviors of double-gate vertical MOSFET. The result proves that the performance of n-channel junctionless double-gate vertical MOSFET (n-JLDGVM) is slightly better than the junction double-gate vertical MOSFET (n-JDGVM). Junctionless device exhibits better analog behaviors as the transconductance (gm) is increased by approximately 4%. In term of RF behaviors, the junctionless device exhibits 3.4% and 7% higher cut-off frequency (fT) and gain band-width product (GBW) respectively over the junction device.

Performance analysis of ultrathin junctionless double gate vertical MOSFETs K. E. Kaharudin; Z. A. F. M. Napiah; F. Salehuddin; A. S. M. Zain; Ameer F. Roslan
Bulletin of Electrical Engineering and Informatics Vol 8, No 4: December 2019
Publisher : Institute of Advanced Engineering and Science

The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.

Performance analysis of ultrathin junctionless double gate vertical MOSFETs K. E. Kaharudin; Z. A. F. M. Napiah; F. Salehuddin; A. S. M. Zain; Ameer F. Roslan
Bulletin of Electrical Engineering and Informatics Vol 8, No 4: December 2019
Publisher : Institute of Advanced Engineering and Science

The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.

Performance analysis of ultrathin junctionless double gate vertical MOSFETs K. E. Kaharudin; Z. A. F. M. Napiah; F. Salehuddin; A. S. M. Zain; Ameer F. Roslan
Bulletin of Electrical Engineering and Informatics Vol 8, No 4: December 2019
Publisher : Institute of Advanced Engineering and Science

The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.

Optimization of 16 nm DG-FinFET using L25 orthogonal array of taguchi statistical method Ameer F. Roslan; F. Salehuddin; A.S.M. Zain; K.E. Kaharudin; I. Ahmad
Indonesian Journal of Electrical Engineering and Computer Science Vol 18, No 3: June 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v18.i3.pp1207-1214

The impact of the optimization using Taguchi statistical method towards the electrical properties of a 16 nm double-gate FinFET (DG-FinFET) is investigated and analyzed. The inclusion of drive current (ION), leakage current (IOFF), and threshold voltage (VTH) as part of electrical properties presented in this paper will be determined by the amendment of six process parameters that comprises the polysilicon doping dose, polysilicon doping tilt, Source/Drain doping dose, Source/Drain doping tilt, VTH doping dose, VTH doping tilt, alongside the consideration of noise factor in gate oxidation temperature and polysilicon oxidation temperature. Silvaco TCAD software is utilized in this experiment with the employment of both ATHENA and ATLAS module to perform the respective device simulation and the electrical characterization of the device. The output responses obtained from the design is then succeeded by the implementation of Taguchi statistical method to facilitate the process parameter optimization as well as its design. The effectiveness of the process parameter is opted through the factor effect percentage on Signal-to-noise ratio with considerations towards ION and IOFF. The most dominant factor procured is the polysilicon doping tilt. The ION and IOFF obtained after the optimization are 1726.88 μA/μm and 503.41 pA/μm for which has met the predictions of International Technology Roadmap for Semiconductors (ITRS) 2013.

Comparative high-k material gate spacer impact in DG-FinFET parameter variations between two structures Ameer F. Roslan; F. Salehuddin; A.S. M. Zain; K.E. Kaharudin; I. Ahmad; H. Hazura; A.R. Hanim; S.K. Idris
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 2: May 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i2.pp573-580

This paper investigates the impact of the high-K material gate spacer on short channel effects (SCEs) for the 16 nm double-gate FinFET (DG-FinFET), where depletion-layer widths of the source-drain corresponds to the channel length. Virtual fabrication process along with design modification throughout the study and its electrical characterization is implemented and significant improvement is shown towards the altered structure design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio), all three materials tested being S3N4, HfO2 and TiO2 increases from the respective 60.90, 80.70 and 84.77 to 84.77, 91.54 and 92.69. That being said, the incremental in ratio has satisfied the incremental on the drive current as well as decreases the leakage current. Threshold voltage (VTH) for all dielectric materials have also satisfy the minimum requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.461±12.7% V. Based on the results obtained, the high-K materials have shown a significant improvement, specifically after the modifications towards the Source/Drain. Compared to the initial design made, TiO2 has improved by 12.94% after the alteration made in terms of the overall ION and IOFF performances through the ION/IOFF ratio value obtained, as well as meeting the required value for VTH obtained at 0.464V. The ION from high-K materials has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.

Title

Found 6 Documents
Search

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Title Search

Found 6 Documents Search

Abstract

Abstract

Abstract

Abstract

Abstract

Abstract

Title

Found 6 Documents
Search