Julius Han Loong Teo
Universiti Tenaga Nasional

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Configurations of memristor-based APUF for improved performance Julius Han Loong Teo; Noor Alia Noor Hashim; Azrul Ghazali; Fazrena Azlee Hamid
Bulletin of Electrical Engineering and Informatics Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (635.38 KB) | DOI: 10.11591/eei.v8i1.1401

Abstract

The memristor-based arbiter PUF (APUF) has great potential to be used for hardware security purposes. Its advantage is in its challenge-dependent delays, which cannot be modeled by machine learning algorithms. In this paper, further improvement is proposed, which are circuit configurations to the memristor-based APUF. Two configuration aspects were introduced namely varying the number of memristor per transistor, and the number of challenge and response bits. The purpose of the configurations is to introduce additional variation to the PUF, thereby improve PUF performance in terms of uniqueness, uniformity, and bit-aliasing; as well as resistance against support vector machine (SVM). Monte Carlo simulations were carried out on 180 nm and 130 nm, where both CMOS technologies have produced uniqueness, uniformity, and bit-aliasing values close to the ideal 50%; as well as SVM prediction accuracies no higher than 52.3%, therefore indicating excellent PUF performance.
Configurations of memristor-based APUF for improved performance Julius Han Loong Teo; Noor Alia Noor Hashim; Azrul Ghazali; Fazrena Azlee Hamid
Bulletin of Electrical Engineering and Informatics Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (1009.692 KB) | DOI: 10.11591/eei.v8i1.1401

Abstract

The memristor-based arbiter PUF (APUF) has great potential to be used for hardware security purposes. Its advantage is in its challenge-dependent delays, which cannot be modeled by machine learning algorithms. In this paper, further improvement is proposed, which are circuit configurations to the memristor-based APUF. Two configuration aspects were introduced namely varying the number of memristor per transistor, and the number of challenge and response bits. The purpose of the configurations is to introduce additional variation to the PUF, thereby improve PUF performance in terms of uniqueness, uniformity, and bit-aliasing; as well as resistance against support vector machine (SVM). Monte Carlo simulations were carried out on 180 nm and 130 nm, where both CMOS technologies have produced uniqueness, uniformity, and bit-aliasing values close to the ideal 50%; as well as SVM prediction accuracies no higher than 52.3%, therefore indicating excellent PUF performance.
Configurations of memristor-based APUF for improved performance Julius Han Loong Teo; Noor Alia Noor Hashim; Azrul Ghazali; Fazrena Azlee Hamid
Bulletin of Electrical Engineering and Informatics Vol 8, No 1: March 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (1009.692 KB) | DOI: 10.11591/eei.v8i1.1401

Abstract

The memristor-based arbiter PUF (APUF) has great potential to be used for hardware security purposes. Its advantage is in its challenge-dependent delays, which cannot be modeled by machine learning algorithms. In this paper, further improvement is proposed, which are circuit configurations to the memristor-based APUF. Two configuration aspects were introduced namely varying the number of memristor per transistor, and the number of challenge and response bits. The purpose of the configurations is to introduce additional variation to the PUF, thereby improve PUF performance in terms of uniqueness, uniformity, and bit-aliasing; as well as resistance against support vector machine (SVM). Monte Carlo simulations were carried out on 180 nm and 130 nm, where both CMOS technologies have produced uniqueness, uniformity, and bit-aliasing values close to the ideal 50%; as well as SVM prediction accuracies no higher than 52.3%, therefore indicating excellent PUF performance.
Ring oscillator physically unclonable function using sequential ring oscillator pairs for more challenge-response-pairs Julius Han Loong Teo; Noor Alia Nor Hashim; Azrul Ghazali; Fazrena Azlee Hamid
Indonesian Journal of Electrical Engineering and Computer Science Vol 13, No 3: March 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v13.i3.pp892-901

Abstract

The ring oscillator physically unclonable function (ROPUF) is one of the several types of PUF that has great potential to be used for security purposes. An alternative ROPUF design is proposed with two major differences. Firstly, the memristor is included in the ring oscillators as it is claimed to produce a more random oscillation frequency. Other reasons are its memory-like properties and variable memristance, relative compatibility with CMOS, and small size. Secondly, a different method of generating the response is implemented whereby a sequence of selection of ring oscillator pairs are used to generate a multiple bit response, rather than using only one ring oscillator pair to generate a single bit response. This method significantly expands the set of challenge-response pairs. The proposed memristor-based ROPUF shows 48.57%, 51.43%, and 51.43% for uniqueness, uniformity, and bit-aliasing, respectively. Also, modelling by support vector machine (SVM) on the proposed memristor-based ROPUF only shows 61.95% accuracy, thereby indicating strong resistance against SVM.