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Pui Mun Lo
Universiti Sains Malaysia
Electrical & Electronics Engineering

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A FPGA threshold-based fall detection algorithm for elderly fall monitoring with verilog Pui Mun Lo; Azniza Abd Aziz
Bulletin of Electrical Engineering and Informatics Vol 10, No 5: October 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v10i5.3152

Abstract

Fall is one of the leading causes of accidental or unintentional injury deaths worldwide due to serious injuries such as head traumas and hip fractures. As life expectancy improved, the rapid increase in aging population implied the need for the development of vital sign detector such as fall detector to help elderly in seeking for medical attention. Immediate rescue could prevent victims from the risk of suspension trauma and reduce the mortality rate among elderly population due to fall accident effectively. This paper presents the development of FPGA-based fall detection algorithm using a threshold-based analytical method. The proposed algorithm is to minimize the rate of false positive fall detection proposed from other researchers by including the non-fall events in the data analysis. Based on the performance evaluation, the proposed algorithm successfully achieved a sensitivity of 97.45% and specificity of 97.38%. The proposed algorithm was able to differentiate fall events and non-fall events effectively, except for fast lying and fall that ending with sitting position. The proposed algorithm shows a good result and the performance of the proposed algorithm can be further improved by using an additional gyroscope to detect the posture of the lower body part.
Co-Authors Azniza Abd Aziz