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All Journal Indonesian Journal of Electrical Engineering and Informatics (IJEEI)
Wan Irma Idayu Restu
Universiti Kebangsaan Malaysia
Computer Science & IT Electrical & Electronics Engineering

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Design and Analysis of High Gain Low Power CMOS Comparator Labonnah Farzana Rahman; Mamun Bin Ibne Reaz; Wan Irma Idayu Restu; Mohammad Marufuzzaman; Lariyah Mohd Sidek
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 6, No 4: December 2018
Publisher : IAES Indonesian Section

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.52549/ijeei.v6i4.816

Abstract

The comparator is the most significant component of the analog-to-digital converter, voltage regulator, switching circuits, communication blocks etc. Depending on the various design schemes, comparator performance varied upon target applications. At present, low power, high gain, area efficient and high-speed comparator designed methods are necessary for complementary metal oxide semiconductor (CMOS) industry. In this research, a low power and high gain CMOS comparator are presented which utilized two-stage differential input stages with replication of DC current source to achieve higher gain, higher phase margin, higher bandwidth, and lower power consumption. The simulated results showed that, by using a minimum power supply of 1.2 V, the comparator could generate higher gain 77.45 dB with a phase margin of 60.08°. Moreover, the modified design consumed only 2.84 µW of power with a gain bandwidth of 30.975 MHz. In addition, the chip layout area of the modified comparator is found only 0.0033 mm2.
Co-Authors Labonnah Farzana Rahman Lariyah Mohd Sidek Mamun Bin Ibne Reaz Mohammad Marufuzzaman