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All Journal International Journal of Electrical and Computer Engineering TELKOMNIKA (Telecommunication Computing Electronics and Control) Bulletin of Electrical Engineering and Informatics Jurnal Informatika Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Indonesian Journal of Electrical Engineering and Computer Science
Mamun Bin Ibne Reaz
Universiti Kebangsaan Malaysia
Computer Science & IT Electrical & Electronics Engineering

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 1 
Review of IDS Develepment Methods in Machine Learning Abdulla Aburomman; Mamun Bin Ibne Reaz
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 5: October 2016
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (104.397 KB) | DOI: 10.11591/ijece.v6i5.pp2432-2436

Abstract

Due to the rapid advancement of knowledge and technologies, the problem of decision making is getting more sophisticated to address, therefore the inventing of new methods to solve it is very important. One of the promising directions in machine learning and data mining is classifier combination. The popularity of this approach is confirmed by the still growing number of publications. This review paper focuses mainly on classifier combination known also as combined classifier, multiple classifier systems, or classifier ensemble. Eventually, recommendations and suggestions have also included.
Integrated Vehicle Accident Detection and Location System Md. Syedul Amin; Mamun Bin Ibne Reaz; Salwa Sheikh Nasir
TELKOMNIKA (Telecommunication Computing Electronics and Control) Vol 12, No 1: March 2014
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.12928/telkomnika.v12i1.13

Abstract

Many accident victim lives could have been saved if vehicle accident information could be intimated to an evergencey rescue center automatically. This paper proposes an accident detection and location system by determining the deceleration and data fusion from accelerometers and GPS. The bias, drift and noise errors of accelerometers and GPS outage limitation are overcome by integrating with Kalman filter. The test result shows the correct deceleration for accident detection and location. The proposed system will be able to overcome the limitations of GPS/IMU and save valuable human lives.
Design of a low-power compact CMOS variable gain amplifier for modern RF receivers M. J. Alam; Mohammad Arif Sobhan Bhuiyan; Md Torikul Islam Badal; Mamun Bin Ibne Reaz; Noorfazila Kamal
Bulletin of Electrical Engineering and Informatics Vol 9, No 1: February 2020
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (470.963 KB) | DOI: 10.11591/eei.v9i1.1468

Abstract

The demand for portability has speeded up the design of low-power electronic communication devices. Variable gain amplifier (VGA) is one of the most vulnerable elements of every modern receiver for the proper baseband processing of the signal. CMOS VGAs are generally suffered from low bandwidth and small gain range. In this research, a two-stage class AB VGA, each stage comprising of a direct transconductance amplifier and a linear transimpedance amplifier, is designed in Silterra 0.13-μm CMOS utilizing Mentor Graphics environment. The post-layout simulation results reveal that the VGA design achieves the widest bandwidth of more than 200 MHz and high gain range from -33 to 32 dB. The VGA dissipates only 2mW from a single 1.2 V DC supply. The core chip area of the VGA is also only 0.026 mm2 which is also the lowest compared to recent researches. Such a VGA will be a very useful module for all modern communication devices.
Design and Analysis of High Gain Low Power CMOS Comparator Labonnah Farzana Rahman; Mamun Bin Ibne Reaz; Wan Irma Idayu Restu; Mohammad Marufuzzaman; Lariyah Mohd Sidek
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 6, No 4: December 2018
Publisher : IAES Indonesian Section

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.52549/ijeei.v6i4.816

Abstract

The comparator is the most significant component of the analog-to-digital converter, voltage regulator, switching circuits, communication blocks etc. Depending on the various design schemes, comparator performance varied upon target applications. At present, low power, high gain, area efficient and high-speed comparator designed methods are necessary for complementary metal oxide semiconductor (CMOS) industry. In this research, a low power and high gain CMOS comparator are presented which utilized two-stage differential input stages with replication of DC current source to achieve higher gain, higher phase margin, higher bandwidth, and lower power consumption. The simulated results showed that, by using a minimum power supply of 1.2 V, the comparator could generate higher gain 77.45 dB with a phase margin of 60.08°. Moreover, the modified design consumed only 2.84 µW of power with a gain bandwidth of 30.975 MHz. In addition, the chip layout area of the modified comparator is found only 0.0033 mm2.
Improved data storage performance based modified-SPEED algorithm Mamun Bin Ibne Reaz; Araf Farayez
Jurnal Informatika Vol 15, No 2 (2021): May 2021
Publisher : Universitas Ahmad Dahlan

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.26555/jifo.v15i2.a20610

Abstract

With the rising demand for smart devices and smart home systems, automation and activity prediction has become a vital aspect of people's everyday lives. Researchers have focused on developing approaches that detect user activity patterns and used them to predict future actions. One such system is Modified Sequence Prediction via Enhanced Episode Discovery (M-SPEED), which uses spatiotemporal daily life activities to analyze user behaviors. However, the low accuracy of this algorithm can be a limiting factor inefficient activity prediction. Also, the computational overhead of run time and memory causes this algorithm to show poor performance in large datasets. This research focuses on modifying the M-SPEED algorithm to improve its capability to run on a larger dataset while at the same time improving run time. The accuracy is also improved to make it more effective in real-world applications. Proof of algorithm efficiency is provided to ensure system validity, and simulation is carried out on real-life data. The results demonstrate a 66.69% improvement in cumulative memory efficiency, 37% faster run time, and 8.22% better accuracy confirming the proposal's effectiveness
Advances on CMOS Shift Registers for Digital Data Storage Mohammad Arif Sobhan Bhuiyan; Hasrul Nisham Bin Rosly; Mamun bin Ibne Reaz; Khairun Nisa Minhad; Hafizah Husain
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 5: May 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar

Abstract

The shift register is the heart of the current digital data storage system. Current trends of wireless device designs are to balance the power consumption, cost and portability of the device. The worldwide research is giving emphasize on increasing the amount of memory at minimum possible space to reduce the overall size of the devices now a days. This paper reports a detailed survey on different types of shift registers in CMOS technology from the performance, design and application point of view. It also discusses the technologies available for the design of shift registers with their merits and demerits. This survey will act as a reference for the scientists to design the high-performance memory module. DOI : http://dx.doi.org/10.11591/telkomnika.v12i5.5207
Advances on Low Power Designs for SRAM Cell Labonnah Farzana Rahman; Mohammad F. B. Amir; Mamun Bin Ibne Reaz; Mohd. Marufuzzaman; Hafizah Husain
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 8: August 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v12.i8.pp6063-6082

Abstract

As the development of complex metal oxide semiconductor (CMOS) technology, fast low-power static random access memory (SRAM) has become an important component of many very large scale integration (VLSI) chips. Lot of applications preferred to use the 6T SRAM because of its robustness and very high speed. However, the leakage current has increasing with the increase SRAM size. It consumes more power while in standby condition. The power dissipation has become an importance consideration due to the increase integration, operating speeds and the explosive growth of battery operated appliances. The objective of this paper is to review and discuss several methods to overcome the power dissipation problem of SRAM. Low power SRAM can be produced with improvement in term of power dissipation during the standby condition, write operation and read operation. Discharging and charging of bit lines consumes more power during write ‘0’ and ‘1’compared to read operation. One of the methods to produce low power SRAM design is with make modification circuit at a standard 6T SRAM cell. This modification circuit will help to decrease power dissipation and leakage current. Several method was discussed in this paper for understand the method to produce low power design of SRAM cell. Recommendations for future research are also set out. This review gives some idea for future research to improve the design of low power SRAM cell.
Design of 3-Bit ADC in 0.18 µm CMOS Process Mohammad Marufuzzaman; Syarizal Z. Abidin; Mamun Bin Ibne Reaz; Labonnah Farzana Rahman
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 7: July 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v12.i7.pp5197-5203

Abstract

Analog-to-digital converters (ADCs) are required to convert the real world analog signals into digital signals, as digital signals are more robust and easier to handle. Signal processing is increasingly being done in the digital domain along with the escalating levels of integration have forced ADC to reside on the same chip as digital circuits. The study describes the design method of 3-bit ADC using CEDEC 0.18 μm CMOS process. The designed ADC consists of; voltage divider, comparator and 7-bit encoder circuits. The pre-simulation has done with ELDO simulator with low power supply voltage (VDD) 1.8 V. The simulated results showed that the designed 3-bit ADC is able to convert analog signals to digital signals.
Co-Authors Abdulla Aburomman Araf Farayez Hafizah Husain Hasrul Nisham Bin Rosly Khairun Nisa Minhad Labonnah Farzana Rahman Lariyah Mohd Sidek M. J. Alam Md Torikul Islam Badal Md. Syedul Amin Mohammad Arif Sobhan Bhuiyan Mohammad Arif Sobhan Bhuiyan Mohammad F. B. Amir Mohammad Marufuzzaman Mohammad Marufuzzaman Mohd. Marufuzzaman Noorfazila Kamal Salwa Sheikh Nasir Syarizal Z. Abidin Wan Irma Idayu Restu