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Nia Gella Augoestien
Departemen Ilmu Komputer Dan Elektronika, FMIPA UGM, Yogyakarta
Electrical & Electronics Engineering

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Purwarupa Perangkat Keras untuk Eksekusi Algoritma AES Berbasis FPGA Nia Gella Augoestien; Agfianto Eko Putra
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems) Vol 5, No 2 (2015): October
Publisher : IndoCEISS in colaboration with Universitas Gadjah Mada, Indonesia.

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (851.207 KB) | DOI: 10.22146/ijeis.7644

Abstract

 AES cryptography algorithm is a tool which often using to protect confidentiality of data.Confidentiality of data is principle parameter of data security in various system. Data security achieve by collaborated AES algorithm with another cryptosystem tools. Therefore, limited resource hardware to excecuteAES algorithm is very important.            This research proposed hardware prototype for excecuting AES algorithm based on FPGA. Optimumresource utilizing become basic priority in this design. So that, we are using resource sharing between hardware for encryption and decryption, iteratif architecture on round level, pipeline architecture on transformation level with 32-bit architecture at design to attain optimum resource utilizing.            Hardware prototype in this research use FPGA Xilinx Spartan®-6 (XC6LX16-CS324), encryption and decryption have been done in this hardware prototype. This prototype have 1,94Mbps/Slice hardware efficiency, 308,96Mbps throughput with only using 6% resource that available on this FPGA.
Implementasi Rangkaian CRC (Cyclic Redundancy Check) Generator pada FPGA (Field Programmable Gate Array) Nia Gella Augoestien; Ryan Aditya
IJEIS (Indonesian Journal of Electronics and Instrumentation Systems) Vol 9, No 1 (2019): April
Publisher : IndoCEISS in colaboration with Universitas Gadjah Mada, Indonesia.

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (707.101 KB) | DOI: 10.22146/ijeis.43906

Abstract

  Data integrity in high speed data transmission process is a major requerment that can not be ignored. High speed data transmission is prone to data errors. CRC (Cyclic Redundancy Check) is a mechanism that is often used as a detector errors in data transmission and storage process. When CRC is implemented using embedded software or processor, CRC requires many clock cycles. If CRC Generator implemented in special dedicated hardware, computational time reduced so that it can be met the high speed system communication requirement. This paper propose the design and implementation of CRC generator on FPGA that capable to minimaze computational time. The method is to reduce calculation latency by separating the coefficients of certain digits and calculating directly the result of  polinomial key modulo. CRC Generator in this paper was implemented on Xilinx Spartan®-6 Series (XC6LX16-CS324). The modeling results have succeeded  to finish computation on 1 clock cycle. Hardware eficiency is achieved 0.38 Gbps/Slice, while the throughput is 3,758 Gbps.
Co-Authors Agfianto Eko Putra Ryan Aditya