Article Per Year (5 Year)
p-Index From 2021 - 2026
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This Author published in this journals
All Journal IAES International Journal of Artificial Intelligence (IJ-AI) International Journal of Reconfigurable and Embedded Systems (IJRES)
Druva Kumar Siddaraju
Dayananda Sagar College of Engineering
Computer Science & IT Economics, Econometrics & Finance Engineering

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Design and performance analysis of efficient hybrid mode multi-ported memory modules on FPGA platform Druva Kumar Siddaraju; Roopa Munibyrappa
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 11, No 2: July 2022
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v11.i2.pp115-125

Abstract

The multi-ported memories (MPMs) are essential and are part of the parallel computing system for high-performance features. The MPMs are commonly used in most processors and advanced system-on-chip (SoC) for faster computation and high-speed processing. In this manuscript, efficient MPMs are designed using the integration of hierarchical bank division with xor (HBDX) and bank division with remap table (BDRT) approaches. The BDRT approach is configured using remap table with a hash write controlling mechanism to avoid write conflicts. The different multiple read ports are designed using BDX, and HBDX approaches are discussed in detail. The results of 2W4R and 3W4R memory modules are analyzed in detail concerning chip area, operating frequency (MHz), block random access memories (BRAMs), and throughput (Gbps) for different memory depths on virtex-7 field programmable gate array (FPGA). The 2W4R utilizes 2.27% slices, operates at 268 MHz frequency by consuming 64 BRAMs for 16K memory depth. Similarly, the 3W4R uses 2.28% slices, operates at 250 MHz frequency by consuming 96 BRAMs for 16K Memory depth. The proposed designs are compared with existing MPM approaches with better chip utilization (Slices), frequency, and BRAMs on the same FPGA device.
Deep learning intrusion detection for software-defined networking using synthetic minority oversampling Prajwalasimha Sindugatta Nagaraja; Navya Rajashekara; Pushpa Bangalore Ramesh; Druva Kumar Siddaraju; Santhosh Kumar Ramachandragowda; Trupti Shripad Tagare
IAES International Journal of Artificial Intelligence (IJ-AI) Vol 15, No 4: August 2026
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijai.v15.i4.pp3703-3711

Abstract

This article proposes an advanced method for network intrusion detection using a combination of recurrent neural networks (RNNs), specifically long short-term memory (LSTM), gated recurrent units (GRU), and bidirectional long short-term memory (BiLSTM) models, enhanced by synthetic minority oversampling technique (SMOTE) to address class imbalance in datasets like network security laboratory–knowledge discovery in databases (NSL-KDD). The method aims to accurately classify network traffic by learning temporal patterns of both normal and malicious activities. SMOTE is employed to balance the dataset, ensuring that underrepresented attack types receive adequate model attention, thereby improving model robustness. The proposed models (LSTM, GRU, and BiLSTM) are trained and evaluated on the NSL-KDD dataset, with hyperparameter tuning performed through RandomizedSearchCV for optimal performance. The results show a significant improvement in accuracy, precision, recall, and F1-score, with BiLSTM demonstrating the highest performance, achieving near-perfect classification results (99.5% accuracy). This method not only mitigates the issue of class imbalance but also leverages the power of RNNs for sequence modeling, offering a promising solution for effective intrusion detection in modern networks.
Co-Authors Navya Rajashekara Prajwalasimha Sindugatta Nagaraja Pushpa Bangalore Ramesh Roopa Munibyrappa Santhosh Kumar Ramachandragowda Trupti Shripad Tagare