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All Journal International Journal of Electrical and Computer Engineering Kitektro Jurnal RESTI (Rekayasa Sistem dan Teknologi Informasi) kawanad Jurnal Pengabdian Rekayasa dan Wirausaha

Hubbul Walidainy

Universitas Syiah Kuala

Author-ID : 4116881

Aerospace Engineering Automotive Engineering Chemical Engineering, Chemistry & Bioengineering Computer Science & IT Control & Systems Engineering Economics, Econometrics & Finance Electrical & Electronics Engineering Engineering

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Title

Design of 8-point DFT based on Rademacher Functions Zulfikar Zulfikar; Hubbul Walidainy
International Journal of Electrical and Computer Engineering (IJECE) Vol 6, No 4: August 2016
Publisher : Institute of Advanced Engineering and Science

This paper presents a new circuit design for 8-point DFT algorithm based on product of Rademacher functions. The design has been adopted from the famous 8-point DFT decimation in time which is mainly constructs of two 4-point and four 2-point DFTs. However, the operation of the design circuit is different. It utilized the advantage of Rademacher functions simplicity. Therefore, the proposed design is constructed form the previous design 4-point DFT which is based on product of Rademacher functions [6]. Some analysis upon number types and internal connections to achieve a more efficient circuit have been conducted. As a result, instead of four, the proposed design requires only three 2-point DFT. Several output results of the design DFT have been removed since they are equal in terms of magnitude, two negative circuit are required as a compensation. Moreover, the previous 4-point DFT has been replaced to the efficient one. This circuit is special designed for non stand alone used, the circuit must be integrated inside the proposed 8-point DFT.

An Improved Design of Linear Congruential Generator based on Wordlengths Reduction Technique into FPGA Hubbul Walidainy; Zulfikar Zulfikar
International Journal of Electrical and Computer Engineering (IJECE) Vol 5, No 1: February 2015
Publisher : Institute of Advanced Engineering and Science

This paper exposes an improved design of linear congruential generator (LCG) based on wordlengths reduction technique into FPGA. The circuit is derived from LCG algorithm proposed by Lehmer and the previous design. The wordlengths reduction technique has been developed more in order to simplify further circuit. The proposed design based on the fact that in applications only specific input data were used. Some nets connections between blocks of the circuit are ignored or truncated. Simulations either behavior or timing have been done and the results is similar to its algorithm. Four best Xilinx chips have been chosen to extract comparison data of speed and occupied area. Further comparison of occupied area in terms of flip-flop and full adder has been made. In general, the proposed design overcome the previous published LCG circuit.

Co-Authors Achmad, Ilham Adriman, Ramzi Ahmadiar Ahmadiar Akhyar Bintang Albar, Nizam Ali Djamhuri Andi Risky Maulana Aulia Rahman Fathurrahman Fathurrahman Fauzan Akbarrizky Ferry Ferry Lubis, Rakhmad Syafutra Mahdi Syukri Masri Maulana, Muhammad Iqbal Maya Fitria Melinda Melinda Muhammad Irhamsyah Putra, T. Edisah Ramdhan Halid Siregar Rizal Munadi Saifuddin Muhammad Jalil Syahrial Syahrial Teuku Yuliar Arif Zulfahmi Helmi Zulfikar Zulfikar

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Journal : International Journal of Electrical and Computer Engineering