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Li Hongjuan
Chongqing University of Posts and Telecommunications

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A Low-Voltage High PSRR and High Precision CMOS Bandgap Reference Zhou Qianneng; Xue Rong; Li Hongjuan; Lin Jinzhao; Li Qi; Pang Yu; Li Guoquan
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 5: May 2014
Publisher : Institute of Advanced Engineering and Science

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Abstract

By adopting the technique of pre-regulator, a high PSRR and low temperature coefficient piecewise-linear bandgap reference (BGR) is designed for analog and mixed-signal application in this paper. The piecewise-linear BGR with pre-regulator, which is analyzed and simulated in SMIC 0.18μm CMOS process, has simple circuit architecture. Simulation results show that piecewise-linear BGR with pre-regulator achieves power supply rejection ratio (PSRR) of -102.488dB and -99.73dB, -82.983dB at 10Hz, 100Hz and 1kHz respectively. Piecewise-linear BGR with pre-regulator achieves the temperature coefficient of 2.235 ppm/°C when temperature is in the range from -50°C to 115°C. When power supply voltage VDD changing from 1.2V to 10V, output voltage deviation of piecewise-linear BGR with pre-regulator is only 0.2765mV, but output voltage of piecewise-linear BGR without pre-regulator has a deviation of 38.08mV. DOI : http://dx.doi.org/10.11591/telkomnika.v12i5.4056
Three-Stage Amplifier Adopting Dual-Miller with Nulling-Resistor and Dual-Feedforward Techniques Zhou Qianneng; Li Qi; Li Chen; Lin Jinzhao; Li Hongjuan; Li Yunsong; Pang Yu; Li Guoquan; Cai Xuemei
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 8: August 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v12.i8.pp6055-6062

Abstract

A high-gain wide-bandwidth three-stage amplifier, which employs dual-miller compensation with nulling-resistor and dual-feedforward compensation (DMCNR-DFC), is designed and analyzed in this paper. By adopting the technique of DMCNR-DFC, the designed three-stage amplifier achieves well performance including gain-bandwidth product (GBW) and slew rate (SR). The improved DMCNR-DFC three-stage amplifier is designed and simulated in 0.5μm BCD process. Simulation results show that DMCNR-DFC three-stage amplifier achieves a dc gain of about 121.1dB and GBW of about 6.1MHz with 52º phase margin using a 5-V power supply voltage.
Co-Authors Cai Xuemei Li Chen Li Guoquan Li Qi Li Yunsong Lin Jinzhao Pang Yu Xue Rong Zhou Qianneng