Article Per Year (5 Year)
p-Index From 2021 - 2026
0.61
P-Index
This Author published in this journals
All Journal Indonesian Journal of Electrical Engineering and Computer Science
Linh Tran
Ho Chi Minh City University of Technology

Published : 3 Documents Claim Missing Document
Claim Missing Document
Check
Articles

Found 3 Documents
Search

 1 
Efficient TCAM design based on dual port SRAM on FPGA Triet Nguyen; Kiet Ngo; Nguyen Trinh; Bao Bui; Linh Tran; Hoang Trang
Indonesian Journal of Electrical Engineering and Computer Science Vol 22, No 1: April 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v22.i1.pp104-112

Abstract

Ternary content addressable memory (TCAM) is a memory that allows high speed searching for data. Not only it is acknowledged as associative memory/storage but also TCAM can compare input searching content (key) against a collection of accumulated data and return the matching address which compatible with this input search data. SRAM-based TCAM utilizes and allocates blocks RAM to perform application of TCAM on FPGA hardware. This paper presents a design of 480×104 bit SRAM-based TCAM on altera cyclone IV FPGA. Our design achieved lookup rate over 150 millions input search data and update speed at 75 million rules per second. The architecture is configurable, allowing various performance trade-offs to be exploited for different ruleset characteristics.
Algorithmic TCAM on FPGA with data collision approach Nguyen Trinh; Anh Le Thi Kim; Hung Nguyen; Linh Tran
Indonesian Journal of Electrical Engineering and Computer Science Vol 22, No 1: April 2021
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v22.i1.pp89-96

Abstract

Content addressable memory (CAM) and ternary content addressable memory (TCAM) are specialized high-speed memories for data searching. CAM and TCAM have many applications in network routing, packet forwarding and Internet data centers. These types of memories have drawbacks on power dissipation and area. As field-programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate TCAM and CAM on FPGA is increasing. Because most FPGAs do not support native TCAM and CAM hardware, methods of implementing algorithmic TCAM using FPGA resources have been proposed through recent years. Algorithmic TCAM on FPGA have the advantages of FPGAs low power consumption and high intergration scalability. This paper proposes a scaleable algorithmic TCAM design on FPGA. The design uses memory blocks to negate power dissipation issue and data collision to save area. The paper also presents a design of a 256 x 104-bit algorithmic TCAM on Intel FPGA Cyclone V, evaluates the performance and application ability of the design on large scale and in future developments.
Parameterized SDRAM-based content-addressable memory on field programmable gate array Binh Dang; Minh Bui; Nguyen Trinh Vu Dang; Linh Tran
Indonesian Journal of Electrical Engineering and Computer Science Vol 31, No 2: August 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v31.i2.pp669-680

Abstract

Contents-addressable memory (CAM) is a special memory that searches the input data with the entire pre-loaded database and generates corresponding address information. CAMs are advancing to be a core technology in computer networking systems. As field programmable gate array (FPGA) is recently being used for network acceleration applications, the demand to integrate CAM on FPGA is increasing. FPGA-based CAMs are divided into three categories of implementation: register-based, block RAM (BRAM)-based, and distributed RAM-based CAM. However, they come with a cost of excessive resource usage. Besides, the collision ratio is high in FPGA-based CAMs, leading to data loss and failure to produce accurate addresses. Synchronous dynamic random-access memory (SDRAM)-based CAMs, benefiting from the features of high density and low price of SDRAM, solve the limitations of FPGA’s on-chip resources. This paper proposes a data collision CAM hardware implementation using modern FPGA’s off-chip SDRAM for data storage. The hardware architecture is customized for massive lookup tables and resource-saving. Furthermore, the architecture is parameterized, which is better for integration. The synthesis results and comparisons show significant advancement compared to other FPGA-based CAM implementations by total reduction of on-chip RAM. The novel architecture shows remarkable improvement in the memory depth and width with the capacity of 128 Mbyte lookup table.
Co-Authors Anh Le Thi Kim Bao Bui Binh Dang Hoang Trang Hung Nguyen Kiet Ngo Minh Bui Nguyen Trinh Nguyen Trinh Vu Dang Triet Nguyen