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Hafizah Husain
Universiti Kebangsaan Malaysia

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Advances on CMOS Shift Registers for Digital Data Storage Mohammad Arif Sobhan Bhuiyan; Hasrul Nisham Bin Rosly; Mamun bin Ibne Reaz; Khairun Nisa Minhad; Hafizah Husain
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 5: May 2014
Publisher : Institute of Advanced Engineering and Science

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Abstract

The shift register is the heart of the current digital data storage system. Current trends of wireless device designs are to balance the power consumption, cost and portability of the device. The worldwide research is giving emphasize on increasing the amount of memory at minimum possible space to reduce the overall size of the devices now a days. This paper reports a detailed survey on different types of shift registers in CMOS technology from the performance, design and application point of view. It also discusses the technologies available for the design of shift registers with their merits and demerits. This survey will act as a reference for the scientists to design the high-performance memory module. DOI : http://dx.doi.org/10.11591/telkomnika.v12i5.5207
Advances on Low Power Designs for SRAM Cell Labonnah Farzana Rahman; Mohammad F. B. Amir; Mamun Bin Ibne Reaz; Mohd. Marufuzzaman; Hafizah Husain
Indonesian Journal of Electrical Engineering and Computer Science Vol 12, No 8: August 2014
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v12.i8.pp6063-6082

Abstract

As the development of complex metal oxide semiconductor (CMOS) technology, fast low-power static random access memory (SRAM) has become an important component of many very large scale integration (VLSI) chips. Lot of applications preferred to use the 6T SRAM because of its robustness and very high speed. However, the leakage current has increasing with the increase SRAM size. It consumes more power while in standby condition. The power dissipation has become an importance consideration due to the increase integration, operating speeds and the explosive growth of battery operated appliances. The objective of this paper is to review and discuss several methods to overcome the power dissipation problem of SRAM. Low power SRAM can be produced with improvement in term of power dissipation during the standby condition, write operation and read operation. Discharging and charging of bit lines consumes more power during write ‘0’ and ‘1’compared to read operation. One of the methods to produce low power SRAM design is with make modification circuit at a standard 6T SRAM cell. This modification circuit will help to decrease power dissipation and leakage current. Several method was discussed in this paper for understand the method to produce low power design of SRAM cell. Recommendations for future research are also set out. This review gives some idea for future research to improve the design of low power SRAM cell.
Co-Authors Hasrul Nisham Bin Rosly Khairun Nisa Minhad Labonnah Farzana Rahman Mamun Bin Ibne Reaz Mohammad Arif Sobhan Bhuiyan Mohammad F. B. Amir Mohd. Marufuzzaman