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K. H. Chong
Universiti Tenaga Nasional

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Influence of optimization of control factors on threshold voltage of 18 nm HfO2/TiSi2 NMOS Norani Atan; Burhanuddin Bin Yeop Majlis; Ibrahim Bin Ahmad; K. H. Chong
Indonesian Journal of Electrical Engineering and Computer Science Vol 14, No 1: April 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v14.i1.pp295-302

Abstract

This paper presents the influence of control factors as the process in development of 18 nm gate length NMOS transistor. The threshold voltage (VTH) can be minimized by optimal the control factors. Five control factors were selected through experiments. They are Adjustment VTH Implantation, Compensation Implantation, Compensation Energy Implantation, Source/Drain Implantation and Halo Implantation.  While the two noise factors were introduced which are Phosphor Silicate Glass (PSG) temperature and Boron Phosphor Silicate Glass (BPSG) temperature to complete the combination with five control factors in process of Taguchi method L27 orthogonal array. The purpose of this research is to find the best value of interaction between combination controls factors and noise factors to achieve the best point of threshold voltage.  In CMOS design, the threshold voltage is the benchmarking of physical parameter for determining the functional of transistor. The Virtual Wafer Fabrication SILVACO software was used to fabricate the 18 nm NMOS device. Hafnium Oxide (HfO2) and Titanium dioxide (TiO2) were utilized as the high-K materials and the Titanium Silicide (TiSi2) was utilized as metal gate. The statistics data are from the signal noise ratio (SNR) with nominal-the best (NTB) and the analysis of variance (ANOVA) of L27 orthogonal array are executed to minimize the variance of threshold voltage. The results show that the optimization and interaction method is achieved to perform the threshold voltage value with least variance  is 0.3055 volts while the target value that is 0.302 ± 12.7% volts from value recommendation by the International Roadmap for Semiconductor prediction 2012.
Analysis the Effect of Control Factors Optimization on the Threshold Voltage of 18 nm PMOS Using L27 Taguchi Method Norani Atan; Burhanuddin Yeop Majlis; Ibrahin Ahmad; K. H. Chong
Indonesian Journal of Electrical Engineering and Computer Science Vol 10, No 3: June 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v10.i3.pp934-942

Abstract

This research paper is about the investigation of Halo Implantation, Halo Implantation Energy, Halo Tilt, Compensation Implantation and Source/Drain Implantation. They are types of control factors that used in achievement of the threshold voltage value. To support the successfully of the threshold voltage (VTH) producing, Taguchi method by using L27 orthogonal array was used to optimize the control factors variation. This analysis has involved with 2 main factors which are break down into five control factors and two noise factors. The five control factors were varied with three levels of each and the two noise factors were varied with two levels of each in 27 experiments. In Taguchi method, the statistics data of 18 nm PMOS transistor are from the signal noise ratio (SNR) with nominal-the best (NTB) and the analysis of variance (ANOVA) are executed to minimize the variance of threshold voltage. This experiment implanted by using Virtual Wafer Fabrication SILVACO software which is to design and fabricate the transistor device. Experimental results revealed that the optimization method is achieved to perform the threshold voltage value with least variance and the percent, which is only 2.16%. The threshold voltage value from the experiment shows -0.308517 volts while the target value that is -0.302 volts from value of International Technology Roadmap of semiconductor, ITRS 2012. The threshold voltage value for 18 nm PMOS transistor is well within the range of -0.302 ± 12.7% volts that is recommendation by the International Roadmap for Semiconductor prediction 2012.
Co-Authors Burhanuddin Bin Yeop Majlis Burhanuddin Yeop Majlis Ibrahim Bin Ahmad Ibrahin Ahmad Norani Atan