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Burhanuddin Yeop Majlis
Universiti Kebangsaan Malaysia

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Optimization of KOH etching process for MEMS square diaphragm using response surface method Norliana Yusof; Badariah Bais; Burhanuddin Yeop Majlis; Norhayati Soin; Jumril Yunas
Indonesian Journal of Electrical Engineering and Computer Science Vol 15, No 1: July 2019
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v15.i1.pp113-121

Abstract

KOH wet etching is widely used in realizing MEMS diaphragm due to its low cost, safe and easy handling. However, wet etching process parameters need to be studied thoroughly in order to realize the desired shape and size of MEMS devices. This paper presents the numerical study and optimization of KOH etching process parameters using the response surface method (RSM). Face central composite design (FCC) of RSM was employed as the experimental design to analyze the result and generate a mathematical prediction model. From the analysis, the temperature was identified as the most significant process parameter that affects the etching rate, thus affecting the thickness and size of the diaphragm. The results of RSM prediction for optimization were applied in this study. Particularly, 45% of KOH concentration, temperature of 80°C, 1735 µm2 of mask size, and 7.2 hours of etching time were implemented to obtain a square MEMS diaphragm with thickness of 120 µm and size of 1200 µm2. The results of RSM based optimization method for KOH wet etching offers a quick and effective method for realizing a desired MEMS device.
Analysis the Effect of Control Factors Optimization on the Threshold Voltage of 18 nm PMOS Using L27 Taguchi Method Norani Atan; Burhanuddin Yeop Majlis; Ibrahin Ahmad; K. H. Chong
Indonesian Journal of Electrical Engineering and Computer Science Vol 10, No 3: June 2018
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijeecs.v10.i3.pp934-942

Abstract

This research paper is about the investigation of Halo Implantation, Halo Implantation Energy, Halo Tilt, Compensation Implantation and Source/Drain Implantation. They are types of control factors that used in achievement of the threshold voltage value. To support the successfully of the threshold voltage (VTH) producing, Taguchi method by using L27 orthogonal array was used to optimize the control factors variation. This analysis has involved with 2 main factors which are break down into five control factors and two noise factors. The five control factors were varied with three levels of each and the two noise factors were varied with two levels of each in 27 experiments. In Taguchi method, the statistics data of 18 nm PMOS transistor are from the signal noise ratio (SNR) with nominal-the best (NTB) and the analysis of variance (ANOVA) are executed to minimize the variance of threshold voltage. This experiment implanted by using Virtual Wafer Fabrication SILVACO software which is to design and fabricate the transistor device. Experimental results revealed that the optimization method is achieved to perform the threshold voltage value with least variance and the percent, which is only 2.16%. The threshold voltage value from the experiment shows -0.308517 volts while the target value that is -0.302 volts from value of International Technology Roadmap of semiconductor, ITRS 2012. The threshold voltage value for 18 nm PMOS transistor is well within the range of -0.302 ± 12.7% volts that is recommendation by the International Roadmap for Semiconductor prediction 2012.
Co-Authors Badariah Bais Ibrahin Ahmad Jumril Yunas K. H. Chong Norani Atan Norhayati Soin Norliana Yusof