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All Journal TELKOMNIKA (Telecommunication Computing Electronics and Control) Journal of Engineering and Technological Sciences Jurnal Filsafat Indonesia JURNAL TEKNOLOGI TECHNOSCIENTIA
Armein Z.R. Langi
ITB
Computer Science & IT Earth & Planetary Sciences Education Engineering

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Journal : Journal of Engineering and Technological Sciences

 1 
Application of Wavelet LPC Excitation Model for Speech Compression Langi, Armein Z.R.
Journal of Engineering and Technological Sciences Vol 40, No 1 (2008)
Publisher : ITB Journal Publisher, LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (233.045 KB) | DOI: 10.5614/itbj.eng.sci.2008.40.1.1

Abstract

This paper presents an application of linear predictive coding (LPC) excitation wavelet models for low bit- rate, high-quality speech compression. The compression scheme exploits the model properties, especially magnitude dependent sensitivity, scale dependent sensitivity, and limited frame length. We use the wavelet model in an open-loop dither based codebook scheme. With t his approach, the compression yields a signal-to-noise ratio of at least 11 dB at rates of 5 kbit/s and.
An LPC Excitation Model using Wavelets Langi, Armein Z.R.
Journal of Engineering and Technological Sciences Vol 40, No 2 (2008)
Publisher : ITB Journal Publisher, LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (191.851 KB) | DOI: 10.5614/itbj.eng.sci.2008.40.2.1

Abstract

This  paper  presents  a  new  model  of  linear  predictive  coding  (LPC) excitation  using  wavelets  for  speech  signals.   The  LPC  excitation   becomes  a linear combination of a set of self-  similar, orthonormal, band-pass signals with time localization and constant bandwidth in a logarithmic scale. Thus, the set of the  coefficients  in  the  linear  combination  represents  the  LPC  excitation.  The discrete  wavelet  transform  (DWT)  obtains  the  coefficients,  having  several asymmetrical  and  non-uniform  distribution  properties  that  are  attractive  for speech processing and compression. The properties include magnitude dependent sensitivity, scale dependent sensitivity, and limited frame length, which can be used  for  having  low  bit-rate  speech.  We  show  that  eliminating  8.97%  highest magnitude  coefficients  degrades  speech  quality  down  to  1.49dB  SNR,  while eliminating  27.51%  lowest  magnitude  coefficient  maintain  speech  quality  at  a level of 27.42 dB SNR. Furthermore eliminating 6.25% coefficients located at a scale associated with 175-630 Hz band severely degrades speech quality down to 4.20 dB SNR. Finally, our results show that optimal frame length for telephony applications is among 32, 64, or 128 samples.
A Hardware Architecture of a Counter-Based Entropy Coder Langi, Armein Z.R.
Journal of Engineering and Technological Sciences Vol 44, No 1 (2012)
Publisher : ITB Journal Publisher, LPPM ITB

Show Abstract | Download Original | Original Source | Check in Google Scholar | Full PDF (331.814 KB) | DOI: 10.5614/itbj.eng.sci.2012.44.1.3

Abstract

This paper describes a hardware architectural design of a real-time counter based entropy coder at a register transfer level (RTL) computing model. The architecture is based on a lossless compression algorithm called Rice coding, which is optimal for an entropy range of bits per sample. The architecture incorporates a word-splitting scheme to extend the entropy coverage into a range of  bits per sample. We have designed a data structure in a form of independent code blocks, allowing more robust compressed bitstream. The design focuses on an RTL computing model and architecture, utilizing 8-bit buffers, adders, registers, loader-shifters, select-logics, down-counters, up-counters, and multiplexers. We have validated the architecture (both the encoder and the decoder) in a coprocessor for 8 bits/sample data on an FPGA Xilinx XC4005, utilizing 61% of F&G-CLBs, 34% H-CLBs, 32% FF-CLBs, and 68% IO resources. On this FPGA implementation, the encoder and decoder can achieve 1.74 Mbits/s and 2.91 Mbits/s throughputs, respectively. The architecture allows pipelining, resulting in potentially maximum encoding throughput of 200 Mbit/s on typical real-time TTL implementations. In addition, it uses a minimum number of register elements. As a result, this architecture can result in low cost, low energy consumption and reduced silicon area realizations. 
Co-Authors Abbas, Muhammad Fadhl Adit Kurniawan Adit Kurniawan Bambang Riyanto Bambang Riyanto Trilaksono Dimitri Mahayana Eko Marpanaji Johan, Meliana Christianti