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All Journal Pixel : Jurnal Ilmiah Komputer Grafis Power Elektronik : Jurnal Orang Elektro
Agung Wirjawan
Sekolah Tinggi Teknologi Mandala
Computer Science & IT Control & Systems Engineering Education Electrical & Electronics Engineering Energy Engineering

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Analisis firewall sebagai bandwidth limiter dan network security menggunakan pfsense Agung Wirjawan; Hilman Iskandar; Rahmad Hidayat; Dwiyanto Dwiyanto; Ike Yuni Wulandari; Yudi Herdiana
Pixel :Jurnal Ilmiah Komputer Grafis Vol 16 No 1 (2023): Vol 16 No 1 (2023): Jurnal Ilmiah Komputer Grafis
Publisher : STEKOM PRESS

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.51903/pixel.v16i1.1003

Abstract

Internet connections that are not always stable and data security is not maintained from various threats from outside attacks in the form of hackers, crackers, viruses, and so on are the main problems for every client. Using the pfSense analysis method, this study aims to address the above bandwidth management and network security issues. The pfSense analysis that the researchers carried out included an analysis of total bandwidth usage, data security, and information for each client on the P3DW Internet network (Center for Regional Revenue Management) Bandung III Soekarno-Hatta City. The results of the analysis concluded that pfSense can work as a firewall that functions as a bandwidth limiter and network security. The level of client satisfaction increases with the infrastructure designs being tested. With a web GUI that makes it easy for users to configure, the basic system used is FreeBSD which is open-source, making pfSense able to be an alternative choice for building a firewall that is reliable, flexible, and economical.
REDUKSI RUGI-RUGI PENSAKLARAN PADA KONVERTER DC-DC ZETA DENGAN TEKNIK ZERO VOLTAGE TRANSITION Anung -; Givy Devira Ramady; Muchamad Sobri Sungkar; Yoddy Agung Nuhgraha; Agung Wirjawan
Power Elektronik : Jurnal Orang Elektro Vol 12, No 1 (2023): POWER ELEKTRONIK
Publisher : Politeknik Harapan Bersama Tegal

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.30591/polektro.v12i1.4378

Abstract

This paper presents a dc-dc ZETA converter with reduced switching loses at the main switch. Reducing switching loses is obtained by application of a resonance switch, where turn-on by the zero voltage and rising voltage at turn-off is limited by capacitor that it’s placed parallel with main switch. The operational principle of the proposed dc-dc ZETA converter with reduced switching loses has been analyzed under different modes of switching operation. To validate the proposed converter, the implementation is carried out using PSIM software. Simulation result shows that the main switch turn-on at the zero voltage and turn-off at the main switch voltage increase in a quadratic function, so that the result of the voltage and current multiplying is lower, on the other hand the loses of the main switch can be reduced.
Co-Authors Anung - Dwiyanto - Givy Devira Ramady Hilman Iskandar Ike Yuni Wulandari Muchamad Sobri Sungkar Rahmad Hidayat Yoddy Agung Nuhgraha Yudi Herdiana