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All Journal Indonesian Journal of Electrical Engineering and Informatics (IJEEI)
Aaquil Bunglowala
Professor, STME NMIMS Indore, Super Corridor NMIMS, Indore, MP, India
Computer Science & IT Electrical & Electronics Engineering

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Optimized Reversible Logic Multiplexer Designs for Energy-Efficient Nanoscale Computing C.Vijesh Joe; Haewon Byeon; Anand Kumar Singh; C. Ramesh Kumar; Aaquil Bunglowala; Anu Tonk
Indonesian Journal of Electrical Engineering and Informatics (IJEEI) Vol 11, No 3: September 2023
Publisher : IAES Indonesian Section

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.52549/ijeei.v11i3.4367

Abstract

Nano- and quantum-based low-power applications are where reversible logic really shines. By using digitally equivalent circuits with reversible logic gates, energy savings may be achieved. Reducing garbage output and ancilla inputs is a primary emphasis of this study, which aims to lower power consumption in reversible multiplexers. Multiplexers with switchable 2:1, 4:1, and 8:1 ratios may be built using the SJ gate and other simple reversible logic gates. The number of ancilla inputs has been cut in half from four to zero, and the amount of garbage output has been cut in half as well, from eight to three, making the 2:1 multiplexer an improvement over the prior design. New 4:1 multiplexer has 10' ancilla inputs, up from 2' in the previous designs. The proposed 4:1 multiplexer also cuts waste production in half from the current 5-to-6 bins per day. The 8:1 multiplexer has two ancilla inputs and nine trash outputs, while the current architecture only has one of each. The functionality of the VHDL and Xilinx 14.7-coded designs is validated by ISIM simulations.
Co-Authors Anand Kumar Singh Anu Tonk C. Ramesh Kumar C.Vijesh Joe Haewon Byeon