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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Takumi Mizuno
Ritsumeikan University
Economics, Econometrics & Finance

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Empirical analysis of power side-channel leakage of high-level synthesis designed AES circuits Takumi Mizuno; Hiroki Nishikawa; Xiangbo Kong; Hiroyuki Tomiyama
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 12, No 3: November 2023
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v12.i3.pp305-319

Abstract

Many internet of things (IoT) devices and integrated circuit (IC) cards have been compromised by side-channel attacks. Power-analysis attacks, which identify the secret key of a cryptographic circuit by analyzing the power traces, are among the most dangerous side-channel attacks. Gen-erally, there is a trade-off between execution time and circuit area. However, the correlation between security and performance has yet to be determined. In this study, we investigate the cor-relation between side-channel attack resistance and performance (execution time and circuit area) of advanced encryption standard (AES) circuits. Eleven AES circuits with different performances are designed by high-level synthesis and logic synthesis. Of the eleven AES circuits, six are circuits with no side-channel attack countermeasures and five are circuits with masking countermeasures. We employ four metrics based on a T-test to evaluate the side-channel attack resistance. The results based on the correlation coefficient show the correlation between side-channel attack resistance and performance. The correlation varies according to four metrics or masking countermeasure. We argue that designers should change their attitudes towards circuit design when considering security.
Co-Authors Hiroki Nishikawa Hiroyuki Tomiyama Xiangbo Kong