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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Chalampalem, Vijaya Bhaskar
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Economics, Econometrics & Finance

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An efficient high performance reconfigurable canonical sign digit architecture for software defined radio Chalampalem, Vijaya Bhaskar; Pidugu, Munaswamy
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 13, No 1: March 2024
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v13.i1.pp25-32

Abstract

Software defined radios (SDRs) are highly motivated for wireless device modelling due to their flexibility and scalability over alternative wireless design options. The evolutionary structure of finite impulse response (FIR) filters was designed for a proposed reconfigurable canonical sign digit (CSD) approach. Considering the complex trade-off, this is accomplished with many FIR taps, which is a challenging assignment. On the baseband processing side, design is given with parameterization-controlled FIR filter tap selection. Optimal processing models to overcome the reconfigurable design issues associated with the SDR system for a multi-standard wireless communication system root cosine filter standard are often used to implement multiple FIR channelization topologies, each of which is tied to a particular in-phase and quadrature (IQ) symbol. Additionally, it demonstrates the viability of using a multi-modulation baseband modulator in the SDR system for next-generation wireless communication systems to maximise adaptability with the least amount of computational complexity overhead. The proposed multiplier-less FIR filter-based reconfigurable baseband modulator, according to the experimental results, offers a 6% complexity reduction and a 47% improvement in performance efficiency over the current SDR system.
Pipelined reconfigurable architecture for 5G software-defined radio systems Chalampalem, Vijaya Bhaskar; Pidugu, Munaswamy; Nagaraju, Sanacarapu
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp320-327

Abstract

The filters are used to allow a specific band of frequencies. In a wireless communication, the filter is used to select the frequency of operation with a narrow or broad band. As the generations increase the amount of data handled increases drastically. 5G data rate can be significantly deliver up to 20 Gigabits per second while 4G communication data rate is handled in the order of 100 Megabits per second. Now the challenge becomes processing data at such a speed with low power and low area specifications. The filters that can configure themselves as per the data received are reconfigurable filters so that the bandwidth is saved. Also, when the pipelining is introduced, the reconfigurable filter improves the performance of the design. This paper details about the pipelined reconfigurable finite impulse response (RFIR) filter with the simplest algorithm with auto updating capability. The design is modelled in Verilog hardware description language (HDL) language, synthesized for Cyclone III field-programmable gate array (FPGA). The results prove that the proposed filter increases only slightly with respect to delay and power dissipation with a trade off in area and maximum possible clock frequency.
Co-Authors Nagaraju, Sanacarapu Pidugu, Munaswamy