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All Journal International Journal of Reconfigurable and Embedded Systems (IJRES)
Nagaraju, Sanacarapu
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Economics, Econometrics & Finance

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Pipelined reconfigurable architecture for 5G software-defined radio systems Chalampalem, Vijaya Bhaskar; Pidugu, Munaswamy; Nagaraju, Sanacarapu
International Journal of Reconfigurable and Embedded Systems (IJRES) Vol 14, No 2: July 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijres.v14.i2.pp320-327

Abstract

The filters are used to allow a specific band of frequencies. In a wireless communication, the filter is used to select the frequency of operation with a narrow or broad band. As the generations increase the amount of data handled increases drastically. 5G data rate can be significantly deliver up to 20 Gigabits per second while 4G communication data rate is handled in the order of 100 Megabits per second. Now the challenge becomes processing data at such a speed with low power and low area specifications. The filters that can configure themselves as per the data received are reconfigurable filters so that the bandwidth is saved. Also, when the pipelining is introduced, the reconfigurable filter improves the performance of the design. This paper details about the pipelined reconfigurable finite impulse response (RFIR) filter with the simplest algorithm with auto updating capability. The design is modelled in Verilog hardware description language (HDL) language, synthesized for Cyclone III field-programmable gate array (FPGA). The results prove that the proposed filter increases only slightly with respect to delay and power dissipation with a trade off in area and maximum possible clock frequency.
Co-Authors Chalampalem, Vijaya Bhaskar Pidugu, Munaswamy