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All Journal International Journal of Electrical and Computer Engineering Bulletin of Electrical Engineering and Informatics
Sahel, Zahra
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Computer Science & IT Electrical & Electronics Engineering

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Design and performance evaluation of a high-efficiency circular microstrip patch antenna for RFID applications at 900 MHz Sahel, Zahra; Habibi, Sanae; Bendali, Abdelhak; ALtalqi, Fatehi; Mouhib, Omar; Habibi, Mohamed
Bulletin of Electrical Engineering and Informatics Vol 14, No 3: June 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/eei.v14i3.9110

Abstract

This study presents a high-efficiency circular microstrip patch antenna designed for radio frequency identification (RFID) applications simulation results illustrate the performance of a circular microstrip patch antenna operating at 900 MHz. Microstrip antennas are renowned for their ability to meet the requirements of compact, lightweight designs, ensuring compatibility, and ease of integration. This research focuses on the development of a circular microstrip antenna, formed as a circular patch on a 0.035 mm thick FR-4 substrate. The design was realized using a substrate with a relative permittivity (εr) of 4.3, a loss tangent (tan δ) of 0.021 and a substrate height (h) of 1.6 mm. The antenna dimensions are small, measuring 58×45 mm, with a circular patch radius of 17 mm. The antenna operates over a frequency range from 0.5 GHz to 2 GHz. Key performance parameters include a return loss of -49.8 dB, a wide bandwidth of 150 MHz, a voltage standing wave ratio (VSWR) of 1.009, a gain of 2.161 dB, and a directivity of 2.200 dBi. Antenna design and simulation were carried out using computer simulation technology (CST) Studio Suite Software, specifically adapted to RFID applications.
Efficient high-gain low-noise amplifier topologies using GaAs FET at 3.5 GHz for 5G systems Zarrik, Samia; Bendali, Abdelhak; Fadlaoui, Elmahdi; Benkhadda, Karima; Habibi, Sanae; Kobbi, Mouad El; Sahel, Zahra; Habibi, Mohamed; Hadjoudja, Abdelkader
International Journal of Electrical and Computer Engineering (IJECE) Vol 15, No 4: August 2025
Publisher : Institute of Advanced Engineering and Science

Show Abstract | Download Original | Original Source | Check in Google Scholar | DOI: 10.11591/ijece.v15i4.pp3833-3842

Abstract

Achieving a gain greater than 18 dB with a noise figure (NF) below 2 dB at 3.5 GHz remains a formidable challenge for low-noise amplifiers (LNAs) in sub-6 GHz 5G systems. This study explores and evaluates various LNA topologies, including single-stage designs with inductive source degeneration and cascade configurations, to optimize performance. The single-stage topology with inductive source degeneration achieves a gain of 18.141 dB and an NF of 1.448 dB, while the cascade-stage common-source low-noise amplifier with inductive degeneration achieves a gain of 32.714 dB and a noise figure of 1.563 dB. These results underscore the importance of GaAs FET technology in meeting the demanding requirements of 5G systems, specifically in the 3.5 GHz frequency band. The advancements demonstrated in gain, noise figure, and linearity affirm the viability of optimized LNA topologies for high-performance 5G applications, supporting improved signal quality and reliability essential for modern telecommunication infrastructure.
Co-Authors ALtalqi, Fatehi Bendali, Abdelhak Benkhadda, Karima Fadlaoui, Elmahdi Habibi, Sanae Hadjoudja, Abdelkader Kobbi, Mouad El Mohamed Habibi Mouhib, Omar Zarrik, Samia